Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit

Abstract

Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.

Description

FIELD OF THE INVENTION [0001] The present invention is directed towards method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit. BACKGROUND OF THE INVENTION [0002] The use of configurable integrated circuits (“IC's”) has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (“FPGA”). An FPGA is a field programmable IC that has an internal array of logic circuits (also called logic blocks) that are connected together through numerous interconnect circuits (also called interconnects). In an FPGA, the internal array of logic and interconnect circuits is typically surrounded by input / output blocks. Like some other configurable IC's, the logic and interconnect circuits of an FPGA are configurable. [0003]FIG. 1 illustrates an array structure 100 of a prior art FPGA. As shown in this figure, the array 100 includes numerous logic circuits 105 and interconnect circuits 110. In this ...

AI Technical Summary

Benefits of technology

The patent describes a method for connecting nodes in a configurable array using different sets of connections. The method calculates a metric score for each set of connections to determine their quality, and selects the best set to connect the nodes. This approach allows for efficient and flexible connection of nodes in the array.

Problems solved by technology

This requirement makes the connection architecture illustrated in FIG. 2 inefficient and expensive as each connection requires the use of transistor switching logic.

Also, the connection architecture illustrated in FIG. 2 is not designed to optimize the number of CLB's reachable from any given CLB.

Such cycles are undesirable as they come at the expense of reachability of other CLB's.

The uniform connection architecture of FIG. 2 is also inefficient as it provides more ways than necessary for reaching one CLB from another CLB.

This redundancy is undersirable as it comes at the expense of reachability of other CLB's.

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