Heat spreader for a multi-chip package

Abstract

Embodiments of a heat spreader and an assembly including such a heat spreader are disclosed. The heat spreader includes a stiffening member, which in one embodiment comprises a wall extending from a lower surface of the heat spreader. The wall may be coupled with a substrate, and the addition of this wall may decrease warpage of the substrate and increase package stiffness. The wall may be located between adjacent integrated circuit die that are disposed on the substrate. Other embodiments are described and claimed.

Description

FIELD OF THE INVENTION[0001]The disclosed embodiments relate generally to the cooling of integrated circuit (IC) devices, and more particularly to a heat spreader for use in multi-chip packages.BACKGROUND OF THE INVENTION[0002]Multi-chip assemblies can provide greater integration and enhanced function in a single package. Integration of IC devices fabricated by different process flows into a single package is possible, and can pave the way for system-in-package (SIP) solutions. In addition to the aforementioned benefits, these SIP or multi-chip packages may exhibit reduced form factors, perhaps including both a smaller overall height as well as a smaller footprint—e.g., the surface area occupied by the package on a next-level component, such as a circuit board—as compared to a similar system having multiple, separate components mounted on a circuit board or other substrate.[0003]One challenge facing multi-chip package designers is cooling these devices during operation. Heat removal...

AI Technical Summary

Problems solved by technology

One challenge facing multi-chip package designers is cooling these devices during operation.

A failure to adequately remove heat from a multi-chip package during operation may lead to reliability and performance deficiencies, and perhaps device failure.

Issues that may arise in designing a cooling solution for a multi-chip package include mismatches in the coefficient of thermal expansion (CTE), thermally induced stresses (especially where low-k dielectric materials and / or lead-free interconnects are employed) and associated substrate and / or die warpage, delamination at thermal interfaces, compatibility with existing assembly processes and tools, integration of two or more die having differing process flows and perhaps varying thicknesses and sizes, and cost.

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