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Solder bump on a semiconductor substrate

a semiconductor substrate and shielding technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical devices, etc., can solve problems such as stress and oxidation of bond pads, and achieve the effect of preventing the oxidation of copper bond pads

Inactive Publication Date: 2009-02-05
JENG SHIN PUU +4
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010]It is therefore an object of the invention to provide a solder bump on a semiconductor substrate and fabrication method thereof. The invention can further prevent the copper bond pad from oxidation in a thermal ambient.
[0011]Another object of the invention is to reduce the stresses created by the package of the integrated circuit chip.

Problems solved by technology

There are, however, still some problems regarding bond pad oxidation and stress.

Method used

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  • Solder bump on a semiconductor substrate
  • Solder bump on a semiconductor substrate
  • Solder bump on a semiconductor substrate

Examples

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Embodiment Construction

[0021]FIG. 1a shows a semiconductor substrate 100 having integrated circuits. At least one dielectric layer 102 and top copper pad 104 are formed on the semiconductor substrate 100. The dielectric layer 102 comprises a low-k material with a dielectric constant less than 3.2, for example an organic polymer based dielectric or an inorganic material such as a carbon-doped oxide or fluorinated silicate glass. Wiring interconnects (not shown) comprising copper are formed within the dielectric layer 102. Top copper pad 104 is disposed, e.g., by damascene technology, within the dielectric layer 102 and serves as a bond pad to connect internal integrated circuits formed on the semiconductor substrate 100 and external circuits. The top copper pad 104 is substantially coplanar with the dielectric layer 102. A protective layer 106 is formed on the dielectric layer 102 and the top copper pad 104. For example, a silicon nitride layer having a thickness of about 300 to about 1000 Å, preferably 75...

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Abstract

A solder bump on a semiconductor substrate is provided. The solder bump has a semiconductor substrate with a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further has a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This patent application is a Divisional of co-pending application Ser. No. 11 / 347,378, filed on Feb. 6, 2006 and entitled “SOLDER BUMP ON A SEMICONDUCTOR SUBSTRATE,” for which priority is claimed under 35 U.S.C. § 120; the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to semiconductor fabrication, in particular, to solder bumps on a semiconductor substrate and fabrication methods thereof.[0004]2. Brief Discussion of the Related Art[0005]The reduction of the feature sizes of semiconductor devices using advanced semiconductor techniques, such as high-resolution lithography and directional etching, have dramatically increased the device packing density on integrated circuit chips formed on a substrate. However, as device packing density increases, the number of electrical metal interconnect layers on the chip must be increased to eff...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/48
CPCH01L23/3192H01L24/03H01L2924/0002H01L2924/01033H01L2924/01019H01L2924/01006H01L2924/14H01L2924/05042H01L2924/014H01L2924/0105H01L24/05H01L24/11H01L24/12H01L2224/0401H01L2224/05082H01L2224/05558H01L2224/05572H01L2224/05624H01L2224/05647H01L2224/13022H01L2224/13099H01L2224/131H01L2924/01013H01L2924/01014H01L2924/01015H01L2924/01022H01L2924/01027H01L2924/01028H01L2924/01029H01L2924/01047H01L2924/00014H01L2224/05552
Inventor JENG, SHIN-PUUTSAI, HAO-YIHOU, SHANG-YUNCHEN, HSIEN-WEITSAI, CHIA-LUN
Owner JENG SHIN PUU