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Method to Improve Ferroelectric Memory Performance and Reliability

a ferroelectric memory and reliability technology, applied in the direction of information storage, static storage, digital storage, etc., can solve the problems of fram memory cells not being able to meet the needs of traditional memory types, fram memory cells facing new problems, and fram memory cells remaining in the same data sta

Inactive Publication Date: 2009-11-12
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

One aspect of power consumption in integrated circuits is the power consumption of memory cells.
Unfortunately, the performance and density of flash memory and other wide spread commercially available non-volatile memory sources lag behind that of volatile memory.
Due to the use of a ferroelectric material rather than traditional dielectrics, reliability of FRAM memory cells face new problems not present in traditional memory types.
One such problem occurs when FRAM memory cells remain in the same data state for a prolonged period of time.
This preference for a particular state drives an increase in signal margin loss over time, resulting in device degradation and reliability concerns.

Method used

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  • Method to Improve Ferroelectric Memory Performance and Reliability
  • Method to Improve Ferroelectric Memory Performance and Reliability
  • Method to Improve Ferroelectric Memory Performance and Reliability

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Embodiment Construction

[0023]The present invention will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale.

[0024]FIG. 1A shows an exemplary FRAM memory cell. This cell comprises a ferroelectric capacitor 100 with a first terminal coupled to a plate line 104 and a second terminal coupled to a transistor 101. The transistor is further coupled to a bit line 102 and a word line 103 at its gate. When a voltage greater than the threshold voltage of the transistor is applied to the word line 103 the transistor turns on, coupling the ferroelectric capacitor 100 to the bit line 102. The bit line 102 is further coupled to a sense amplifier 105 which is coupled to a reference voltage source 106. The reference voltage source 106 provides a reference voltage. The sense amplifier 105 compares the reference voltage to the output of the bit line...

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Abstract

One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This is a division of application Ser. No. 11 / 965,350, filed Dec. 27, 2007, the entire disclosure of which is hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]In recent years the market of the semiconductor industry has grown considerably for supplying integrated chips to companies which manufacture portable electronic device. The integrated chips used to make these portable electronic device, such as cell phones, PDAs, laptop computers and the like, are mostly made in emerging technology nodes. This is because emerging technology nodes offer higher density chips with greater performance and lower power consumption. These qualities are important to portable electronic devices which are continually striving to offer greater functionality while relying on relatively small energy sources (e.g., batteries). The demand for these products has driven the industry to devote many resources to developing low power integrated chips,...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C11/22G11C11/24G11C11/42
CPCG11C11/22
Inventor RODRIGUEZ, JOHN
Owner TEXAS INSTR INC
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