Test equipment and semiconductor device

Abstract

An interface circuit is connected to an ATE via a test control bus BUS3 that differs from main buses, receives a control signal output from the ATE, and controls multiple BIST circuits according to the control signal. Furthermore, a DUT is configured such that a test result signal specified by the control signal can be read by the ATE via the test control bus. A BISI synchronous control unit generates a first control signal for individually controlling the multiple BIST circuits included in the DUT, and a second control signal for reading the test result signal generated by the BIST circuit, and supplies these signals to the DUT via the test control bus.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a test technique for a semiconductor device.[0003]2. Description of the Related Art[0004]In order to test a semiconductor device at low cost, a BIST (Built-In Self Test) circuit is employed. The BIST circuit thus employed provides diagnosis of defective portions and a quality check by writing and reading a defined input / output signal at a low speed to / from a device under test (which will be referred to as a “DUT” hereafter) without involving high-cost semiconductor automatic test equipment (which will be referred to as “ATE” hereafter). In particular, with regard to BISTs for memory circuits and logic circuits, many actual results and research results have accumulated. BISTs for such circuits have been implemented in production tests. The standard IEEE1149.1 was formulated by the JTAG (Joint Test Action Group) in 1990. This standard integrates the method for the boundary scan test and th...

AI Technical Summary

Benefits of technology

[0031]With, such an embodiment, an integrated interface is provided for the multiple BIST circuits, thereby allowing the multiple BIST circuits included in the DUT to be

Problems solved by technology

In general, ATE devices that are capable of inputting/outputting signals at a high speed is costly according to the signal input/output speed, leading to increased test cost.

1. In a case in which there are multiple BISTs according to respective control specifications independent of one another, there are differences in the control commands and the expected value comparison procedure among the BIST circuits, leading to a complicated control operation of the ATE for the BISTs provided by the DUT. This leads to increased test time and redundant test resources.

2. In a case in which the BIST circuits perform operations linked together or synchronized with one anothe

Images