Low depth programmable priority encoders

Abstract

An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to priority encoders generally and, more particularly, to a method and / or apparatus for implementing low depth programmable priority encoders.BACKGROUND OF THE INVENTION

[0002] Priority encoders are useful logic to determine arbitrated situations that can be used in various applications. A priority encoder transfers only a single logical one bit in a highest priority position within an N-bit request signal (i.e., R) to a corresponding position an N-bit output signal (i.e., Z). Programmable priority encoders operate as multiple parallel encoders under the control of a priority signal (i.e., P).

[0003] Referring to FIG. 1, a netlist of a conventional programmable priority encoder (PPE) circuit 20 is shown. The circuit 20 uses a ripple carry implementation that creates a long timing path 22. For an N-bit signal R, the long path 22 causes a 2N−3 Boolean gate delay through the circuitry. Hence, the circuit 20 has difficulty operating ...

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