Protecting the footprint of memory transactions from victimization

Abstract

A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

Description

PRIORITY CLAIM[0001]This application is a continuation of U.S. patent application Ser. No. 13 / 967,853 entitled “PROTECTING THE FOOTPRINT OF MEMORY TRANSACTIONS FROM VICTIMIZATION,” filed on Aug. 15, 2013, the disclosure of which is incorporated herein by reference in its entirety for all purposes.BACKGROUND OF THE INVENTION[0002]The present invention relates generally to data processing and, in particular, to storage accesses to the distributed shared memory system of a data processing system.[0003]A conventional multiprocessor (MP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latenc...

AI Technical Summary

Benefits of technology

This patent is related to a processing unit that includes a cache memory. The cache memory is organized in groups called congruence classes. When the cache receives a memory access request that specifies a specific cache line, the cache checks if it already has that line in its cache. If there is, it updates the order in which the cache lines are replaced. This way, the cache can improve its performance by replacing cache lines that are less likely to be needed in the future.

Problems solved by technology

A conflict occurs between two memory accesses when they are to the same memory location and at least one of them is a write and there is no means to ensure the ordering in which those accesses occur.

These include, among others, (1) the possibility of deadlock when a given thread holds more than one lock and prevents the forward progress of other threads and (2) the performance cost of lock acquisition when the lock may not have been strictly necessary because no conflicting accesses would have occurred to the shared data.

If a conflict occurs in the transaction footprint, the transaction is aborted and possibly restarted.

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