Methods for dicing a compound semiconductor wafer, and diced wafers and die obtained thereby

a compound semiconductor and die technology, applied in semiconductor lasers, semiconductor/solid-state device details, radiation controlled devices, etc., can solve problems such as mechanical defects in dies, difficult to achieve very smooth side walls of dies,

Inactive Publication Date: 2015-04-09
AVAGO TECH WIRELESS IP SINGAPORE PTE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The plasma etching method produces dies with side wall variations less than 10 microns, enabling precise passive alignment and allowing for the creation of non-rectangular shapes, thereby reducing mechanical defects and improving the accuracy of die placement in arrays.

Problems solved by technology

With respect to scribing and breaking or sawing, it is difficult to achieve side walls for the dies that are very smooth.
Rather, the side walls of the dies are often rough or jagged, which can eventually lead to mechanical defects being formed in the dies (e.g., through chipping or cracking).

Method used

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  • Methods for dicing a compound semiconductor wafer, and diced wafers and die obtained thereby
  • Methods for dicing a compound semiconductor wafer, and diced wafers and die obtained thereby
  • Methods for dicing a compound semiconductor wafer, and diced wafers and die obtained thereby

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Embodiment Construction

[0022]In accordance with the invention, methods are provided that use masking techniques and plasma etching techniques to dice a compound semiconductor wafer. Using these systems and methods allow compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment mechanism to precisely align features of the die with an external device. Illustrative embodiments of the methods, systems and the resulting dies will now be described with reference to the figures, in which like reference numerals represent like elements, components or features.

[0023]FIG. 1 illustrates a pictorial diagram of a plasma etching chamber that may be used to perform plasma etching to dice compoun...

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Abstract

Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation application of application Ser. No. 13 / 758,265, filed on Feb. 4, 2013, originally entitled “METHODS FOR DICING A COMPOUND SEMICONDUCTOR WAFER, AND DICED WAFERS AND DIE OBTAINED THEREBY,” which has been allowed and which is hereby incorporated by reference herein in its entirety.TECHNICAL FIELD OF THE INVENTION[0002]The invention relates to semiconductor wafers and processes. More particularly, the invention relates to methods for dicing a compound semiconductor wafer, and the diced wafers and die obtained by those methods.BACKGROUND OF THE INVENTION[0003]Semiconductor fabrication processes are multi-step processes that are used to create integrated circuits (ICs) that are used in a variety of applications. The process begins with the epitaxial growth of the wafer followed by many processing steps, such as deposition processes (e.g., chemical vapor deposition, molecular beam epitaxy, physical vapor deposi...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L25/16H01S5/40H01S5/02H01L25/04H01L31/0232H01S5/02375
CPCH01L25/167H01L25/042H01S5/4087H01S5/0203H01L31/02327H01L21/78H01L21/6836H01L2221/68336H01L21/30621H01S5/423H01L31/02325H01L31/18H01L2924/0002Y10S438/975H01S5/02375H01L2924/00H01L23/544H01L21/50H01L21/302
InventorPEH, CHEE SIONGNG, CHIEW HAIMCINTYRE, DAVID G.
OwnerAVAGO TECH WIRELESS IP SINGAPORE PTE