Method and apparatus for reducing cache thrashing

a cache memory device and cache technology, applied in the field of cache memory devices, can solve the problems of significantly reducing cache performance and increasing cache misses, and achieve the effect of improving cache performance and reducing cache trashing

Inactive Publication Date: 2005-03-29
AVAGO TECH INT SALES PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Generally, a method and apparatus are disclosed for adaptively decreasing cache trashing in a cache memory device. The present invention improves performance of a cache by automatically detecting thrashing of a set and ...

Problems solved by technology

If there are not enough frames in a set to store all the blocks that map to the set that are currently in use by a program, one or more frames must be evicted prematurely (i.e., ...

Method used

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  • Method and apparatus for reducing cache thrashing
  • Method and apparatus for reducing cache thrashing
  • Method and apparatus for reducing cache thrashing

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Embodiment Construction

FIG. 1 illustrates a cache thrashing reduction system 100 in accordance with the present invention. The present invention improves performance of an N-way associative cache 110 by automatically detecting thrashing in a set, such as sets 2 and 3, and then reducing thrashing in the thrashed set(s) by providing one or more augmentation frames 150 as additional cache space. In this manner, the trashed sets can remain in the cache longer, improving their hit rate. The augmentation frames 150 are obtained, for example, by mapping the blocks that map to a thrashed set to one or more additional, less utilized sets. While the present invention is illustrated with a two-way set associative instruction cache that has two frames at each set address, the present invention may be incorporated into all cache organizations (data or instruction), as would be apparent to a person of ordinary skill in the art. The cache thrashing reduction system 100 and cache 110 can be part of a digital signal proce...

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Abstract

A method and apparatus are disclosed for adaptively decreasing cache trashing in a cache memory device. Cache performance is improved by automatically detecting thrashing of a set and then providing one or more augmentation frames as additional cache space. In one embodiment, the augmentation frames are obtained by mapping the blocks that map to a thrashed set to one or more additional, less utilized sets. The disclosed cache thrashing reduction system initially identifies a set that is likely to be experiencing thrashing, referred to herein as a thrashed set. Once thrashing is detected, the cache thrashing reduction system selects one or more additional sets to augment a thrashed set, referred to herein as the augmentation sets. In this manner, blocks of main memory that are mapped to a thrashed set are now mapped to an expanded group of sets (the thrashed set and the augmentation sets). Finally, when the augmentation sets are no longer likely to be needed to decrease thrashing, the augmentation set(s) are disassociated from the thrashed set(s).

Description

FIELD OF THE INVENTIONThe present invention relates generally to cache memory devices, and more particularly, to methods and apparatus for adaptively decreasing cache trashing in a cache memory device.BACKGROUND OF THE INVENTIONProcessors often use a cache to improve performance and decrease system costs. Caches temporarily store recently accessed information (blocks of instructions or data) in a small memory that is faster to access than a larger main memory. Caches are effective because a block that has been accessed once is likely to be accessed soon again or is often near a recently accessed block. Thus, as a task executes, the working set of a task (the instructions and data currently required for the task) is stored in the cache in the event that the information may be accessed again. A cache typically maps multiple blocks of information from the main memory into one place in a cache, typically referred to as a “set.” A “block” refers to the minimum unit of information that ca...

Claims

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Application Information

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IPC IPC(8): G06F12/12
CPCG06F12/121G06F12/12
Inventor DWYER, HARRYFERNANDO, JOHN SUSANTHA
Owner AVAGO TECH INT SALES PTE LTD
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