Method of forming a conformal spacer adjacent to a gate electrode structure

Abstract

In a process for forming L-shaped sidewall spacers for a conducive line element, such as a gate electrode structure, the sacrificial spacers are formed of a material having a similar etch behavior as the material of the finally obtained L-shaped spacer, thereby improving tool utilization and reducing process complexity compared to conventional processes. In one particular embodiment, a spacer layer stack is provided having a first etch stop layer, a first spacer layer, a second etch stop layer, and a second spacer layer, wherein the first and second spacer layers are comprised of silicon nitride.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of highly conformal spacer elements, also referred to as L-shaped spacers, during the manufacturing of conductive lines, such as a gate electrode of a field effect transistor.[0003]2. Description of the Related Art[0004]In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and power consumption. Typically, the gate electrode of a field effect transistor may be considered as a conductive line, which is comprised in standard CMOS technology of highly doped polysilicon including a metal silicide region, wherein the lateral extension of the conductive line substantially determines the length of a conductive channel being formed in a s...

AI Technical Summary

Problems solved by technology

Although the above-described sidewall spacer technique is very efficient in the fabrication of CMOS devices having a gate length well beyond 0.2 μm, it turns out that for smaller feature sizes the formation of relatively bulky sidewall spacers may be disadvantageous in view of thermal stress exerted to the gate electrode and caused by the formation of the sidewall spacers.

Additionally, bulky sidewall spacers may not provide the required flexibility in designing the lateral dopant profile of the drain and source regions and the corresponding extension regions connecting to the channel region.

Consequently, additional reactive gases or other precursors required for the appropriate etch chemistry have to be provided in combination with a suitable etch tool, thereby contributing to process complexity.

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