Driving circuit with impedence calibration
a driving circuit and impedence technology, applied in the direction of pulse generators, electrical apparatus, electric pulse generators, etc., can solve the problems of inability to apply the tail current source connection reference ground, still suffer from an over-large power consumption, etc., and achieve the effect of less power consumption and the same performan
Patent Information
- Authority / Receiving Office
- US · United States
- Patent Type
- Patents(United States)
- Current Assignee / Owner
- Publication Date
- 2011-08-02
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a driver, and more particularly, to a low power, high speed driving circuit with auto-calibration functionality.
[0003] 2. Description of the Prior Art
[0004] As the resolution of image sensors or display increases, the data rate of becomes very high. As a result, a requirement for a high speed driver with superior performance grows. Among all kinds of high speed drivers, a low voltage differential signal (LVDS) technique is frequently utilized due to a lower electromagnetic interference (EMI), a lower power consumption and a better signal integrity than those of a conventional CMOS full swing driver. Please refer to FIG. 1, which is a diagram of a conventional LVDS driver for driving a pair of loads R1 and R2. The conventional LVDS driver 100 is composed of two PMOS transistors M1, M2, two NMOS transistors M3, M4, and two constant current sources I1 and I2 connected to a reference supply vo...
Examples
Embodiment Construction
[0016]Please refer to FIG. 4, which shows a driving unit (e.g., an LDVS driver) according to an embodiment of the present invention. The exemplary driving unit 400 includes, but is not limited to, a first bias component RA, a second bias component Re, a first metal-oxide-semiconductor (MOS) transistor MN1, a second MOS transistor MN2, a third MOS transistor MN3, and a fourth MOS transistor MN4, where the first, second, third, and fourth MOS transistors MN1-MN4 have the same conductive type. By way of example, rather than limitation, the first and second bias components RA and RB are implemented using resistors, and the first, second, third, and fourth MOS transistors are N-channel metal-oxide-silicon (NMOS) transistors for a lower threshold voltage. However, this is for illustrative purposes only. Any driving circuit that follows the exemplary circuit architecture shown in FIG. 4 to configure interconnections of implemented bias components and MOS transistors falls within the scope ...