Electronic device, system on chip and method for monitoring a data flow

a technology of electronic devices and data flow, applied in the field of electronic devices, system on chips and a monitoring method of data flow, can solve the problem of not having a guarantee regarding the latency of communication throughput, and achieve the effect of efficient monitoring of data traffi

Active Publication Date: 2011-12-27
SYNOPSYS INC
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0006]It is therefore an object of the invention to provide an electronic device, a system on chip and a method for monitoring a data traffic which enables an efficient monitoring of the data traffic.
[0015]The invention relates to the idea that the bandwidth required for sniffing or monitoring one connection or communication is distributed over multiple lower-bandwidth debug connections or communications instead of one larger-bandwidth debug or monitor connection. In addition, multiple probes can be provided along a connection's or communication path, wherein each probe or monitor can sniff one or more connection or communication. The debug connections may share the resources of the network on chip together with the user resources. Especially if it is difficult and sometimes impossible to setup high bandwidth debug-connections in a network-on-chip NoC resource constrained environment, it is advantageous to schedule more debug connection with lower-bandwidth.

Problems solved by technology

For best effort communication, there is no guarantee regarding the latency of the throughput of the communication.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0027]FIG. 2 shows a block diagram of a system on chip with a network-on-chip interconnect according to a The system on chip according to FIG. 2 substantially corresponds to the system on chip as shown in FIG. 1. The only difference is the provision of a probe P1 which is attached or coupled to the router R2. The probe is able to sniff data like flits, messages, transactions or other granularity depending how much intelligence is built in the probe. Here, as an example the probe can sniff flits. The output of the probe P1 is coupled to the network interface NI2.

[0028]The probe P1 is able to sniff all flits of the connection C when the flits pass the router R2. The sniffed flits are passed to the network interface NI2 and is forwarded to the monitoring service access unit MSA. A debug or monitor connection (or a debug communication path) MC1 from the second network interface NI2 to monitoring service access unit MSA is required in order to transport the data of the probe, i.e. the m...

second embodiment

[0030]FIG. 3 shows a block diagram of a system on chip with a network-on-chip interconnect according to a The system on chip according to FIG. 3 substantially corresponds to the system on chip according to FIG. 2 but comprises multiple probes e.g. all routers can be probed ensuring a full coverage of all possible connections or communication paths to be set up.

[0031]Accordingly, N probes may be present on the path of connection C. Here, a first probe P1 is attached to the router R2 and a second probe P2 is attached to the router R4. Therefore, N debug or monitor connections are required, namely a first debug or monitor connection MC1 and second debug or monitor connection MC2 with the bandwidth BMC1 and BMC2. The first debug or monitor connection MC1 is provided for the data of the first probe and the second debug or monitor connection MC2 is provided for the data of the second probe. By means of the debug or monitor connections, the data from the first and second probe are forward...

third embodiment

[0040]FIG. 4 shows a schematic block diagram of part of a system on chip according to a Here, a first and second router, R1, R2, a first and second network interface, NI1, NI2 and a monitoring service access unit MSA are depicted. Each of the network interfaces NI1, NI2 comprises several buffers B and optionally a combine unit CU1, CU2. The combine units CU1, CU2 serve to combine the data received from the probes or monitors via the routers R1, R2. A queue or buffer B is associated with each of the monitors or probes. The combination units CU12, CU2 serve to combine the data from the queues or buffers B. Preferably, this is performed based on a schedule which may be in synchronization with the data sniffing. In addition or alternatively, the schedule can be performed in space, time or content dimensions.

[0041]The data traffic from the monitors or probes (which each may form part of the monitoring result respectively) arrive at the network interfaces NI1, NI2 such that the combinati...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

An electronic device is provided which comprises a plurality of processing units (IP1-IP6), a network-based inter-connect (N) coupled to the processing units (IP1-IP6) and at least one monitoring unit (P1, P2) for monitoring a data flow of at least one first communication path between the processing units (IP1-IP6) and for forwarding monitoring results at least temporarily via at least two separate communication paths (MC1, MC2).

Description

FIELD OF INVENTION[0001]The invention relates to an electronic device, system on chip and a method of monitoring a data flow.BACKGROUND OF THE INVENTION[0002]Networks on chips NOC proved to be scalable interconnect structures in particular for systems on chip which could become possible solutions for future on chip interconnections between so-called IP blocks, i.e. intellectual property blocks. IP blocks are usually modules on chip with a specific function like CPUs, memories, digital signal processors or the like. The IP blocks communicate with each other via the network on chip. The network on chip is typically composed of network interfaces and routers. The network interfaces serve to provide an interface between the IP block and the network on chip, i.e. they translate the information from the IP block to information which the network on chip can understand and vice versa. The routers serve to transport data from one network interface to another. For best effort communication, t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(United States)
IPC IPC(8): H04L12/26
Inventor GOOSSENS, KEES G. W.CIORDAS, CALINRADULESCU, ANDREI
Owner SYNOPSYS INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap