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SRAM bit cell with reduced bit line pre-charge voltage

a bit cell and pre-charge voltage technology, applied in the field of static random access memory (sram) devices, can solve the problem that data retention requires relatively little power

Active Publication Date: 2015-08-18
NXP USA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, data retention requires relatively little power.

Method used

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  • SRAM bit cell with reduced bit line pre-charge voltage
  • SRAM bit cell with reduced bit line pre-charge voltage
  • SRAM bit cell with reduced bit line pre-charge voltage

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Embodiment Construction

[0015]Embodiments of SRAM memory devices are disclosed that include six transistor (6T) bit cells with bit lines pre-charged to ½ VDD and low VT pass transistors. The bit cells use 50% lower power during read and write operations since the bit lines swing ½ of the supply voltage (VDD) instead of full VDD. Additionally, the bit cells have faster write and pre-charge speeds since bit lines only slew ½ VDD. Bit lines driven with ½ VDD allow faster sensing since the cross coupled p-transistors as well as the cross coupled n transistors of a dynamic sense amplifier can be employed to provide gain. Use of ½ VDD instead of full VDD also reduces power supply noise due to less crowbar current as sensing resolves more quickly. The area required to implement the ½ VDD bit cells in a highly scaled technology is comparable to other 6T bit cells. The ½ VDD bit cells have similar or improved stability as other 6T bit cells. Since more transistors are employed in reading data from the bit cell to c...

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PUM

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Abstract

An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations.

Description

BACKGROUND[0001]1. Field[0002]This disclosure relates generally to semiconductor memory devices, and more specifically, to static random access memory (SRAM) devices.[0003]2. Related Art[0004]Semiconductor memory devices are used in a wide variety of electronic devices such as portable telephones, digital cameras, mobile and stationary computing devices, automobiles, appliances, and other devices.[0005]The key attributes of an SRAM memory are the speed and power of the memory. SRAM memory is often employed when high speed access is required. SRAM memory is a static memory that requires power to be maintained for data retention. However, data retention requires relatively little power. Much of the power dissipated in an SRAM memory relates to the bit lines charging and discharging. Another important aspect of an SRAM is the signal provided to the bit lines by a bit cell during a Read access, that is, how fast that signal is provided and how reliably that signal can be sensed. Another...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C11/412G11C11/419
CPCG11C11/419G11C11/412
Inventor BURNETT, JAMES D.PELLEY, PERRY H.
Owner NXP USA INC