Method for plating using nested plating buses and semiconductor device having the same

Abstract

Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I / O count for a given substrate area and / or reduces the need to have routing on more than one layer of the substrate.

Description

FIELD OF THE INVENTIONThe present invention relates to plating and plated devices in general, and more specifically to plating using nested plating buses and semiconductor devices having such nested plating buses.BACKGROUND OF THE INVENTIONDue to the constant push for smaller and smaller products, it has become common for integrated circuits (ICs) once contained on two or more individual semiconductor die or chips to be combined into a single, larger IC device. For example, traditional microprocessor circuits are being combined on a single chip with digital signal process circuits. These combined ICs have the advantage of better reliability due to fewer total external connections, but have higher input / output (I / O) counts than many of the individual ICs. Often, these combined devices have I / Os in the 200+ range. Additionally, new ICs are being designed "from the ground up" with many advanced features which also result in 200+ I / Os. Thus, high I / O counts are becoming more and more co...

AI Technical Summary

Problems solved by technology

The most expensive individual cost component is the substrate.

One of the limitations of single layer substrates is the restriction in routing electrical connections from the vias to an external plating bus formed at the periphery of the package.

Depending on the capabilities of the substrate manufacturer and on the I / O count of the package, the external plating connections also often directly limit the number of discrete I / O connections possible for single layer substrate packages.

In other words, the need to connect all traces to an external, peripheral plating bus often restricts the routing density for a given size substrate.

Increasing the solder pad and via pitches undesirably increases the size of the substrate and size of the final package, whereas decreasing solder pad and via diameters would undesirably increase the cost to manufacture the substrate and reduce the solder joint strength due to the smaller solder pads.

However, electroless plating is inherently thinner and more porous than electrolytic plating which makes it marginal at preventing oxidation of the underlying copper.

This in turn makes it more difficult to achieve good, reliable bonding onto the plated surfaces.

Consequently, the use of electroless gold plating is limited to special cases where the time and temperature exposures are short and low enough that the resulting oxidation does not impede the creation of reliable bonds.

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