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Integrated memory circuit with redundant circuit and method for substituting memory zone

A redundant memory and memory circuit technology, applied in the direction of static memory, digital memory information, information storage, etc.

Inactive Publication Date: 2008-09-24
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

After or during the burn-in operation, further functional testing of the integrated memory circuit generally takes place, during which, in some cases, further defects occur

Method used

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  • Integrated memory circuit with redundant circuit and method for substituting memory zone
  • Integrated memory circuit with redundant circuit and method for substituting memory zone

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] according to figure 1 Redundant circuits are generally provided on integrated memory chips.

[0027] according to figure 1 The redundant circuit has a fuse storage element 1, which is formed from a fuse circuit 2 and a fuse latch 3.

[0028] The fuse circuit 2 has a first p-channel transistor 4, an n-channel transistor 5 and a laser fuse 6, which are connected in series. The first terminal of the p-channel transistor 4 is connected to the high supply voltage potential V DD , the second terminal of the first p-channel transistor 4 is connected to the first terminal of the n-channel transistor 5 and the second terminal of the n-channel transistor 5 is connected to the laser fuse 6 The first terminal, the second terminal of the laser fuse is connected to a low supply voltage potential, preferably ground potential V GND . Set signal S can be supplied to the control input of the n-channel transistor 5 and reset R can be supplied to the control input of the first p-chann...

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PUM

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Abstract

An integrated memory circuit having a redundancy circuit for replacing a memory area having an address by a redundant memory area assigned to the redundancy circuit and method for replacing a memory area. In one embodiment, the redundancy circuit comprises one or more fuse storage elements in which the address of the memory area which is to be replaced by the redundant memory area can be set, wherein, for the purpose of setting the address, each of the fuse storage elements may be set to a first state by the respective fuse storage element being left unchanged and set to a second state by the respective fuse storage element being permanently changed, an activation fuse storage element for activating the address stored in the fuse storage elements for replacing the memory area with the redundant memory area, and a deactivation storage element for permitting or preventing replacement of the memory area having the address by the redundant memory area, wherein the deactivation storage element is connected to the fuse storage elements in such a way as to prevent replacement of the memory area if each of the fuse storage elements has been permanently changed and set to the second state.

Description

technical field [0001] The present invention relates to an integrated memory circuit with redundant circuits for replacing a memory area with an address by a redundant memory area assigned to the redundant circuit, the invention also relates to an integrated memory circuit for replacing a memory area with an address with a redundant memory area Methods for memory regions. Background technique [0002] Integrated memory circuits, especially DRAM memory circuits, are generally not defect-free after their manufacture, ie, defective memory cells are present throughout the memory chips and, as a result, these memory chips cannot be used. To increase the yield of the integrated memory circuit after manufacture, in the integrated memory circuit, besides the memory area, a redundant memory area is provided. [0003] After manufacture, the entire integrated memory circuit including the redundant memory area is tested, in which case the memory area identified as defective is replaced...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/401G11C7/00G11C29/00
CPCG11C29/838G11C29/812G11C29/787
Inventor P·比尔
Owner INFINEON TECH AG
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