Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals

Abstract

A synchronous mirror delay (300) includes a ring oscillator that generates a plurality of tap clock signals (T1-T7) with one tap clock signal being designated an oscillator clock signal. In response to an input clock signal, a model delay line generates a model delayed clock signal having a model delay relative to the input clock signal. A coarse delay circuit generates a coarse delay count (316) responsive to the oscillator, input, and model delayed clock signals, and activates a coarse delay enable signal responsive to the delay count being equal to a reference count value. A fine delay circuit latches the tap clock signals and develops a fine delay from the latched signals, and activates a fine delay enable signal having the fine delay in response to the coarse delay enable signal. An output circuit generates a delayed clock signal responsive to the coarse and fine delay enable signals going active.

Description

Technical field [0001] The present invention relates generally to integrated circuits, and more specifically, to synchronizing an internal clock signal generated in an integrated circuit with an external clock signal applied to the integrated circuit. Background technique [0002] In a synchronous integrated circuit, the integrated circuit is clocked by an external clock signal and performs operations at a predetermined time, wherein the predetermined time is related to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous storage devices, such as synchronous dynamic random access memory (SDRAM), synchronous static random access memory (SSRAM), and cassette memory such as SLDRAM and RDRAM, as well as other types of integrated circuits , For example, a microprocessor. The timing of synchronizing the external signal of the storage device is determined by the external clock signal, and it is usually necessary to syn...

AI Technical Summary

Problems solved by technology

Also, these large numbers of individual delay stages 110A-N, 116A-N can result in significant power consumption of the SMD 100, which may not be desirable, especially if the synchronous storage device is included in a portable battery powered device

Images