Master latch circuit with signal level displacement for a dynamic flip-flop

Abstract

A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK), resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) and which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (ClkDELAY) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage.

Description

technical field [0001] The present invention relates to a master latch circuit with signal level shifting function for a dynamic flip-flop with minimum signal switching delay. Background technique [0002] US6507228B2 discloses a clock-edge-triggered latch circuit for high-frequency clock signals. A latch circuit includes a signal delay circuit that delays a clock signal occurring at a specific time. Circuit nodes connected downstream are charged according to the data signal occurring during a time window, wherein the time window is adjusted by the delay time. [0003] In digital systems, computing power is limited due to power loss generating digital system heat. Furthermore, especially in mobile digital systems, the power consumption of the components limits the duration of operation. [0004] Therefore, it has been proposed to use multiple operating voltages in digital logic blocks, components in critical signal paths are adapted to use high voltage operating voltages,...

AI Technical Summary

Problems solved by technology

[0017] As shown in Figure 8, by integrating the signal level shift function into the traditional static flip-flop, compared with the traditional edge flip-flop shown in Figure 4 and the image 3 Although the traditional signal level shifting circuit shown can save some chip area and power consumption, the signal delay is basically the sum of the signal delay of the signal level shifting circuit and the signal delay caused by the flip-flop

[0018] due to Figure 7 and similar prior art flip-flops with signal shifting shown in Figure 8 must be supplied with two supply voltages V A , V B , and must comply with a certain minimum distance between components, so the area saved is relatively small and the signal delay is relatively large

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