Method and apparatus for forming a flip chip semiconductor package and method for producing a substrate for the flip chip semiconductor package

Abstract

The present invention provides a detailed specification of the flip-chip package and the molding compound used for the package to a molding flow simulator, and identifies the location of void formation within the package during the molding process. Next, the substrate (124) for packaging is designed with through holes (206) at the positions where the voids are formed. During the molding process, as the molding compound flows between the die and the substrate (124) and forces the air out, the air pockets where the voids form pass through the vias (206) in the lower cavity bar (110) and The vent (116) escapes. Additionally, the lower cavity strip (110) has a downwardly disposed center location (114), which allows air to flow from the through hole (206) to the vent hole (116). Furthermore, because the vias (206) are between 20-30 microns in diameter, more area on the lower surface of the substrate (124) is available for terminals arranged in an array.

Description

technical field [0001] The present invention relates to forming flip-chip semiconductor packages and substrates thereof, and more particularly to molding flip-chip semiconductor packages having substrates. Background technique [0002] A flip-chip semiconductor package is well known as a package in which a raised semiconductor die is flipped over and, after reflow, its pad pattern is directly connected to a corresponding pattern of terminals on a substrate by means of bumps. The die, bumps or interconnects, and the assembly of the substrate are then molded over the substrate to encapsulate the die and bumps in the molding compound. The molded package protects the die and bumps and allows easy handling of the package. In addition, molded packages must be able to withstand a range of operating conditions, including operation at elevated temperatures. [0003] One difficulty when molding a flip chip package is creating a void between the die and the substrate. Voids are air ...

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Problems solved by technology

[0006] Thus, a disadvantage of Weber's method is that air pockets trapped around interconnects located close to the vent can escape through the vent, however, air pockets not located close to the vent are between the semiconductor die and the substrate. keep intercepted

[0007] Another disadvantage of the Weber method is the formation of overflow beads on the bottom surface of the substrate

[0009] A further disadvantage of Weber is the need for a lower cavity bar with overflow channels in it, and because the vent holes in the substrate and the overflow channels of the lower cavity bar must be aligned, making manufacturing complex and costly, and , various molded semiconductor packages require the use of various lower cavity strips

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