Turn-on bus transmitter with controlled slew rate

Abstract

The bus amplifier / driver (40) has an output transistor (M1) controlled by a controllable current source (I1). In the quiescent state, the output transistor is configured as part of a current mirror (M1, M11) used to maintain the gate-source voltage on the output transistor above the threshold voltage of the output transistor, thereby providing fast Connect time. In an active state, the controllable current source provides a substantially constant current to the output transistor to achieve a controllable slew rate, and then reduces the current to the output transistor when a desired output voltage level is reached. To improve power efficiency, a second controllable current source (I2) supplies current to the output load when the desired output voltage is reached. To minimize transients, the Class AB control circuit (710) provides a minimum bias current to the output transistors to prevent the output transistors from turning off when the desired output voltage is reached.

Description

technical field [0001] This invention relates to the field of electronic circuits and, in particular, to amplifiers / drivers with fast on-times and controllable slew rates. Background technique [0002] Figures 1a-1b illustrate a conventional bus driver 10 configured to transmit power and data across a two-wire bus. Figure 1a shows a schematic diagram of the transmitter, and Figure 1b shows the shape of the bus signal. At the beginning, the power switch SupSW is closed and the operation of the amplifier ABamp is disabled by keeping the digital input signal EN low. Thus, the bus voltage V BUSP It is connected to the power supply Vsup, so that power can be delivered to the devices connected to the bus. At time t1, the power switch SupSW is opened, enabling the amplifier to operate by switching the digital input EN high. The amplifier then starts pulling down the bus voltage at a controlled slew rate. Due to the controllable slew rate, the high frequency content of the bus ...

AI Technical Summary

Problems solved by technology

As is known in the art, a limitation of the driver presented in Figure 3 is that this driver can only be used to always pull down the bus voltage to V BUSN , so that it is not possible to obtain other bus level

The second problem is that the connection time is very slow

Therefore, at the beginning, all the driving current I1 has to be used to charge the gate-source capacitance Cgs, resulting in a long turn-on delay

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