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Method of implantation after copper seed deposition

A technology of seeding and implanting, which is applied in the direction of plating, coating, and metal material coating process of superimposed layers, and can solve problems such as wire failure and failure

Inactive Publication Date: 2008-12-31
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The void can eventually grow to a size that causes open-circuit failure of the wire

Method used

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  • Method of implantation after copper seed deposition
  • Method of implantation after copper seed deposition
  • Method of implantation after copper seed deposition

Examples

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Embodiment Construction

[0025] Referring to FIG. 4 , the integrated circuit portion 400 includes a substrate layer 410 , a barrier layer 420 , a seed / barrier interfacial layer 430 , and a seed layer 440 . The substrate 410 can be any variation of the dielectric layer or different layers without diffusion or migration.

[0026] The barrier layer 420 is used to prevent material from diffusing into the substrate layer 410 . The barrier layer 420 can be tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or any other variation of barrier material. In one example, the barrier layer 420 may have a cross-sectional thickness of 30-70 Angstrom. The seed layer 440 may include copper (Cu) or a copper alloy and may have a cross-sectional thickness of 100-300 angstroms.

[0027] In the first exemplary embodiment, the seed / barrier interface layer 430 may include different elements that are implanted to form a mixed region with a uniform distribution of elements. For example, the seed / barrie...

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Abstract

A method of fabricating an integrated circuit may include: forming a barrier layer along sidewalls and bottoms of a via hole; forming a seed layer proximate and conformal to the barrier layer; and forming a proximate and conformal seed layer an implantation layer on the barrier layer and the seed layer. The via hole is used for accommodating the via material to electrically connect the first conductive layer and the second conductive layer.

Description

technical field [0001] The present invention relates generally to an integrated circuit and a method of fabricating an integrated circuit. In particular, the present invention relates to a method of implanting after copper seed deposition. Background technique [0002] A semiconductor device or integrated circuit may contain millions of components such as transistors. Ultra Large Size Integrated (ULSI) circuits may include complementary metal oxide semiconductor (CMOS, complementary metal oxide semiconductor) field effect transistors (FETs). Although existing systems and processes are capable of fabricating millions of integrated circuit devices on an integrated circuit, there is still a need to reduce the feature size of integrated circuit devices, thereby increasing the number of devices on an integrated circuit. However, there are still many factors that make continued miniaturization of integrated circuits difficult. For example, as the size of a via (or channel betwee...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768C23C28/00
CPCH01L21/76846H01L21/76859H01L21/76867H01L21/76871H01L21/768
Inventor S·洛帕京P·R·贝瑟M·S·比伊诺斯基
Owner GLOBALFOUNDRIES INC