Method of specifying pin states for a memory chip

Abstract

This invention discloses a method of specifying pin states for a memory chip having one or more pins. In one embodiment of the invention, the pins are prioritized to obtain a pin order, wherein the pin state of a pin of a higher order dominates the pin state of a pin of a lower order. A number of possible combinations of the pin states are generated for the pins based on the pin order. The possible combinations are presented using a data presentation format. At least one pin of a higher order dominates at least one pin of a lower order when the at least one pin of a higher order is set in a predetermined pin state, such that the number of the possible combinations presented is reduced by neglecting combinations generated by the pins states of the dominated pins.

Description

technical field [0001] The present invention relates to memory chips, and more particularly to a systematic way to fully specify the behavior of memory chips. Background technique [0002] The memory chip has multiple pins with different functions. For example, a known single-port static random access memory (Static Random Access Memory, SRAM) has various pins, for example, a synchronous clock (CLK) pin, a chip enable (chip-enable, CE) pin , Read and write (write-enable, WE) control pin, address (A) pin and data (D) pin. These CLK, CE, WE, A, and D pins receive input signals that affect the operation of the memory chip. It is therefore desirable to provide a library of intellectual property components to indicate how the signal state of these pins affects the behavior of the memory chip. [0003] The pins of the memory chip can be in a normal state or an abnormal state. This normal state includes high and low level signals, which are usually represented by logic "1" and ...

AI Technical Summary

Problems solved by technology

Confusion arises when comparing the correct behavior of simulated modules and memory chips

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