Testing method capable of configuring FPGA interconnection resource with four times

Abstract

The present invention provides a testing method of the FPGA interconnecting resources completed by four times of configuring. The characteristics reside in: the switch matrixes are divided into four kinds: the level, the upright, the left oblique and the right oblique according to the connection direction. In each configuring, the testing circuit is designed according to one connection direction. The switch matrixes are concatenated to form snake shaped testing accesses and each access is added with a testing vector of walk step -1. In the present invention, the testing of the FPGA interconnecting resources is completed effectively, and the a 100% testing coverage rate is achieved, and the connection is easy to realize, also, the times of configuration testing and the testing cost are greatly reduced.

Description

technical field [0001] The invention relates to a test method of an FPGA chip, in particular to a test method for completing FPGA interconnection resources with only four configurations. Background technique [0002] The premise of testing the FPGA is to configure it, design a variety of test circuits and go through multiple configuration-test processes to achieve effective testing of the FPGA. It takes much more time to configure an FPGA than to apply a test vector, so the key to improving the efficiency of FPGA testing is to minimize the number of configurations while ensuring test coverage. [0003] In the actual application of FPGA, the probability of faults occurring in interconnect resources is far greater than that in other logic functions. Therefore, it is of great significance to study the test methods of interconnect resources to improve the yield of FPGA. Foreign countries have conducted research on the testing of FPGA interconnection resources, and proposed a me...

AI Technical Summary

Problems solved by technology

[0004] The technical solution of the present invention is: under the premise that the test coverage rate of interconnection resources reaches 100%, reduce the number of test configurations as far as possible, and provide a test method for completing FPGA interconnection resources with four configurations. From four directions, the connection resource level is connected into a serpentine network, and the step-1 test vector is applied, which overcomes the shortcomings of the previous method that the number of test configurations is large, the switch connection is complicated, and the test vector cannot effectively distinguish the fault location.

Images