FPGA interconnect resource allocation generation method based on reinforcement learning

Abstract

The invention belongs to the technical field of FPGAs and provides an FPGA interconnect resource allocation generation method based on reinforcement learning. Firstly, an interconnect resource model based on the reinforcement learning is constructed, and a state transition matrix and a return function are initialized; then, the state transition matrix and the return function are combined, and according to the interconnect source model, a reinforcement learning training method is adopted to train a strategy; then, a wiring initial state point is set, according to the strategy, allocation traces are finished, and according to the allocation traces, the state transition matrix is updated; finally, the state transition matrix is updated repeatedly until the coverage rate is withdrawn, all allocation traces are summarized and converted to allocation codes, and finally, the interconnect resource allocation is output. According to the FPGA interconnect resource allocation generation method based on the reinforcement learning, by the adoption of a reinforcement learning theory, on the premise that the interconnect resource test coverage rate reaches 100 %, test allocation times are effectively reduced, automatic allocation of the FPGA comprising Global and Local interconnect resources is achieved, the test efficiency is high, and the applicability is good.

Description

technical field [0001] The invention belongs to the field of FPGA technology, and in particular relates to a method for generating FPGA interconnection resource configuration based on reinforcement learning. Background technique [0002] With the rapid development of semiconductor technology, the field programmable gate array (Field Programmable GateArray, hereinafter referred to as FPGA) is becoming more and more integrated, and the scale of internal programmable resources is getting larger and more functions. The accompanying problem is that the circuit structure is becoming more and more complex, the possibility of failure is getting higher and higher, and the requirements for testing technology are getting higher and higher. [0003] Most of the programmable logic resources of SRAM-type FPGA chips are composed of interconnect resources (InterconnectResource, hereinafter referred to as IR) and programmable logic blocks (Configurable Logic Block, hereinafter referred to as...

AI Technical Summary

Problems solved by technology

[0005] The traditional test method is based on the structural characteristics and programmability of the FPGA, and it is manually placed and routed to complete the generation of the test configuration; the efficiency is low, and it can only be used for chips with a specific structure without automatic configuration, which is no longer applicable

The test method is disclosed in the document "A FPGA Local Interconnect Test Method Based on Greedy Strategy [P]. Invention Patent, CN102116840A, 2011-07-06" and the document "Modeling of FPGA Local / Global Interconnect Resource and Derivation of Mini mal Test Configurations" It is only suitable for a small part of Local tests and cannot be used for Global tests

The method disclosed in the document "Interconnection Structure Modeling Method and Interconnection Resource Configuration Vector Automatic Generation Method. Invention Patent, CN103412253B, 2016.01.20" is suitable for Global and Local tests, but the number of configurations is relatively large

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