A Method for Generating FPGA Interconnect Resource Configuration Based on Reinforcement Learning

Abstract

The invention belongs to the field of FPGA technology, and provides a method for generating FPGA interconnect resource configuration based on enhanced learning; firstly, an FPGA interconnect resource model based on enhanced learning is established, and a state transition matrix and a return function are initialized; then, the state transition matrix and the return function are combined , according to the interconnection resource model, use the reinforcement learning training method to train the strategy; then set the initial state point of the wiring, complete the configuration routing according to the strategy, and update the state transition matrix according to the configuration routing; finally update the state transition matrix repeatedly until the coverage Convergence, summarizing all configuration lines, converting them into configuration codes, and finally outputting interconnect resource configurations. The invention adopts the enhanced learning theory, and under the premise that the test coverage rate of interconnection resources reaches 100%, effectively reduces the number of test configurations, realizes the automatic configuration of FPGA including Global and Local interconnection resources, and has high test efficiency and good applicability.

Description

technical field [0001] The invention belongs to the field of FPGA technology, and in particular relates to a method for generating FPGA interconnection resource configuration based on reinforcement learning. Background technique [0002] With the rapid development of semiconductor technology, the field programmable gate array (Field Programmable GateArray, hereinafter referred to as FPGA) is becoming more and more integrated, and the scale of internal programmable resources is getting larger and more functions. The accompanying problem is that the circuit structure is becoming more and more complex, the possibility of failure is getting higher and higher, and the requirements for testing technology are getting higher and higher. [0003] Most of the programmable logic resources of SRAM-type FPGA chips are composed of interconnect resources (InterconnectResource, hereinafter referred to as IR) and programmable logic blocks (Configurable Logic Block, hereinafter referred to as...

AI Technical Summary

Problems solved by technology

[0005] The traditional test method is based on the structural characteristics and programmability of the FPGA, and it is manually placed and routed to complete the generation of the test configuration; the efficiency is low, and it can only be used for chips with a specific structure without automatic configuration, which is no longer applicable

The test method is disclosed in the document "A FPGA Local Interconnect Test Method Based on Greedy Strategy [P]. Invention Patent, CN102116840A, 2011-07-06" and the document "Modeling of FPGA Local / Global Interconnect Resource and Derivation of Mini mal Test Configurations" It is only suitable for a small part of Local tests and cannot be used for Global tests

The method disclosed in the document "Interconnection Structure Modeling Method and Interconnection Resource Configuration Vector Automatic Generation Method. Invention Patent, CN103412253B, 2016.01.20" is suitable for Global and Local tests, but the number of configurations is relatively large

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