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A test structure and method of fpga internal connection resources

A test structure and interconnection technology, applied in the field of test structure of FPGA interconnection resources, can solve the problems of long test time and unfavorable practical application, and achieve the effect of shortening the test time and reducing the number of test configurations.

Inactive Publication Date: 2011-12-21
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the test time of FPGA depends almost entirely on the number of configurations, the test time of this method is too long, which is not conducive to practical application

Method used

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  • A test structure and method of fpga internal connection resources
  • A test structure and method of fpga internal connection resources
  • A test structure and method of fpga internal connection resources

Examples

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Embodiment Construction

[0035] Take the XC3S400 FPGA of the Spartan 3 series of Xilinx as an example. This type of FPGA has 34 rows and 32 columns in total, including two rows and two columns of input and output ports IOB and two columns of block RAM (random access memory). There are eight double long lines and intelligent long lines in the east, west, north and south directions. Among them, the east line and west line are staggered, and the south line and north line are staggered. Column line segment test BIST structure such as Image 6 As shown, the line segment test BIST structure is as follows Figure 7 shown.

[0036]1) the test structure of a kind of FPGA internal connection resource of the present invention, it is a kind of built-in self-test structure, its test pattern generator TPG 1, output response analyzer ORA 2 and tested circuit CUT 10 are all by FPGA internal resources constitute. The entire test structure will be implemented by writing a test configuration program to configure th...

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Abstract

The invention relates to a test structure for interconnect resources in a field programmable gate array (FPGA). The test structure is a built-in self test structure; a test pattern generator (TPG), an output response analyser (ORA) and a circuit under test (CUT) are composed of internal resources of the FPGA; and the whole test structure is realized by writing a test configuration program for configuring the FPGA. A test method for the interconnect resources in the FPGA comprises the following six steps of: 1, arranging configuration logic blocks (CLBs); 2, configuring the TPG; 3, configuring the ORA; 4, configuring the CUT; 5, establishing a readback file by using an FPGA development platform, running the FPGA, reading analysis result data saved in a trigger in the ORA, and detecting and positioning a fault; and 6, repeating the steps 1-5, and completing four-time configuration of dual-long-line resources with CLB rank, intelligent long-line resources, dual-long-line resources without CLB rank and intelligent long-line resources and a final test according to the distribution of the CLBs and the type of the CUT.

Description

technical field [0001] The invention relates to a test structure and method of an FPGA (Field Programmable Gate Array, Field Programmable Gate Array) internal connection resource, and belongs to the technical field of FPGA internal connection testing. Background technique [0002] There are abundant routing resources inside the FPGA device. Taking Xilinx's Spartan 3 series as an example, its wiring resources include long-line resources, intelligent long-line resources, double long-line resources and direct interconnection line resources. [0003] Long-term resources include 24 horizontal long-terms and 24 vertical long-terms. These long wire resources are bidirectional and run through the entire device, such as figure 1 As shown, the outputs of every six interconnect blocks are connected to this routing resource. [0004] There are eight intelligent long-line resources in the east, west, south, and north directions, which are the same length as the long lines. The output...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/319
Inventor 高成俞少华黄姣英郭伟
Owner BEIHANG UNIV
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