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Multichip packaging structure and its production method

A technology of multi-chip packaging and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., and can solve problems such as many system chip mask processes, system chip development obstacles, and low yield rate

Active Publication Date: 2009-10-14
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the system chip has too many mask processes, the manufacturing cost is too high, and the yield rate is too low. Therefore, in actual development, the development of the system chip is still hindered.

Method used

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  • Multichip packaging structure and its production method
  • Multichip packaging structure and its production method
  • Multichip packaging structure and its production method

Examples

Experimental program
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Embodiment Construction

[0027] Figure 1A A schematic top view showing a multi-chip packaging structure according to the first embodiment of the present invention, Figure 1B draw Figure 1A The schematic cross-sectional view of the multi-chip package structure along the line I-I'. Please refer to Figure 1A and Figure 1B , the multi-chip packaging structure 100 of the first embodiment includes a carrier 110 , at least one chip 120 and a chip 130 . Wherein, the carrier 110 is, for example, a substrate, and the collocation of the chip 120 and the chip 130 may be a memory chip, a north bridge chip, a graphics chip, a CPU chip, etc. that are used in conjunction with each other. For example, chip 120 may be a memory chip, and chip 130 may be a graphics chip. The chip 120 is electrically connected to the carrier 110 and disposed on the carrier 110 . The chip 130 is electrically connected to the chip 120 and the carrier 110 , and a part of the chip 130 is disposed on the chip 120 , while other parts of...

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PUM

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Abstract

The invention discloses a multi-chip packaging structure, which includes a carrier, at least one first chip and a second chip. The first chip is electrically connected to the carrier and configured on the carrier. The second chip is electrically connected to the first chip and the carrier, and a part of the second chip is configured on the first chip, while other parts of the second chip are configured on the carrier. In addition, a method for manufacturing a multi-chip packaging structure is also proposed.

Description

technical field [0001] The present invention relates to a semiconductor element and its manufacturing method, and in particular to a multi-chip packaging structure and its manufacturing method. Background technique [0002] In the semiconductor industry, the production of integrated circuits (IC) can be mainly divided into three stages: design of integrated circuits, fabrication of integrated circuits, and packaging of integrated circuits. [0003] In the fabrication of integrated circuits, chips are completed through wafer fabrication, integrated circuit formation, and wafer sawing. The wafer has an active surface, which generally refers to the surface of the wafer with active elements. After the integrated circuit inside the wafer is completed, the active surface of the wafer is also equipped with a plurality of bonding pads, so that the chips formed by dicing the wafer can be electrically connected to the outside through these pads. carrier. The carrier is, for example...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L25/065H01L23/488H01L21/60
CPCH01L2224/16145H01L25/0652H01L2224/16225H01L25/0657H01L2224/48227
Inventor 林有玉温琮毅
Owner VIA TECH INC