Display timing parameter adaptive adjusting method for display control device
An adaptive adjustment and display control technology, applied in static indicators, electrical digital data processing, cathode ray tube indicators, etc., can solve the problem of setting resolution, not actively adjusting the best resolution of the display, and not being able to adjust the resolution And other issues
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[0026] The following embodiments utilize the display control chip realized by FPGA / ASIC, can access the EDID (extended display identification data) of the display through the DDC (display data channel) interface, obtain the timing parameters of the display, and automatically adjust the timing of the output signal according to these parameters parameters to achieve the best match with the monitor.
[0027] The logic block diagram of the display control chip implemented by the FPGA / ASIC is shown in Figure 2, which mainly includes a timing generation unit, a DDC control unit, a video memory control unit, and a hot-plug detection unit. The digital display signal generated by the display control chip is converted into a corresponding standard display signal through the VGA or DVI interface chip, and connected to the display together with two DDC signals. For a display with a DVI interface, a hot plug detection signal HPD will be output to the display control chip.
[0028] The dis...
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