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Memory testing

A technology of memory testing and memory, applied in data processing systems, testing memory in data processing systems to detect memory faults, and can solve problems such as processors cannot handle interrupts

Active Publication Date: 2008-01-09
ARM LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, although these tests can be completed more quickly, the processor still cannot handle any interrupts received during the test and must wait for the test to complete
This is a serious problem in real-time systems where interrupt latency is a critical requirement

Method used

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Experimental program
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Embodiment Construction

[0035] The data processing apparatus 10 of FIG. 1 includes an interrupt controller 20 capable of receiving external interrupts and forwarding at least some of them to a processor 30 and a memory BIST controller 40. It will be appreciated that such integrated circuits 10 typically include many more many circuit elements, but they are omitted from this figure for simplicity and clarity.

[0036] Microprocessor 30 is connected to memory BIST controller 40 via link 50 . This link enables the microprocessor to communicate with the memory BIST controller 40 . Thus, processor 30 can instruct controller 40 to initiate its test of embedded memory 60 at some point in its idle state. The processor 30 can also receive communications from the memory BIST controller 40 telling the processor 30 whether the memory BIST controller has completed its tests and whether there are problems. Processor 30 may also poll BIST controller 40 while waiting for it to complete.

[0037] The interrupt contr...

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Abstract

This application discloses a data processing apparatus comprising: at least one memory; processing logic operable to perform data processing operations on data and operable to access said at least one memory; and memory testing logic operable to perform a transparent algorithm testing routine on said at least one memory, said data processing apparatus impeding said processing logic from accessing said at least one memory while said memory testing logic is performing said testing routine; wherein said processing logic and said memory testing logic are operable to detect a system event, said memory testing logic being operable when performing said testing routine to respond to detection of said system event by stopping said testing routine and restoring said at least one memory to an initial state, said initial state being a state it was in immediately prior to commencement of said testing routine, whereupon said data processing apparatus is operable to allow said processing logic to access said at least one memory.

Description

technical field [0001] The present invention relates to the field of data processing systems. More precisely, the present invention relates to the field of testing memory in data processing systems to detect memory failures. Background technique [0002] It is known to provide data processing systems including memories with a self-test mechanism (sometimes called built-in self-test (BIST), built-in self-test) so that they can perform a self-test or a series of self-tests after the memory circuits have been fabricated. Test to determine if there is a memory fault, which would mean that the circuit should be discarded. It is important that memory circuits should be highly reliable and failed circuits should be identified efficiently. As memory size grows, so does memory as a proportion of the die, and the high transistor density in memories means that these memories are becoming increasingly dense to fail. [0003] One known technique to address this problem is to provide i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/14
CPCG11C2029/0401G11C29/16G06F11/27G06F11/273G11C29/12G11C29/48
Inventor P·S·休斯
Owner ARM LTD