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Parallel interleaver, parallel deinterleaver, and interleave method

A technology of interleaver and row number, which is applied in the field of parallel interleaver to prevent access contention

Inactive Publication Date: 2008-01-30
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since RAM1 is a single-port memory, only one of them can be written.

Method used

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  • Parallel interleaver, parallel deinterleaver, and interleave method
  • Parallel interleaver, parallel deinterleaver, and interleave method
  • Parallel interleaver, parallel deinterleaver, and interleave method

Examples

Experimental program
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Effect test

Embodiment approach 1

[0150] Fig. 21 shows the configuration of an interleaver according to Embodiment 1 of the present invention. The interleaver 100 can execute PIL (Prime Interleaver) in parallel without memory access contention. In this embodiment, to simplify the description, only circuits corresponding to the number of interleaver rows R = 5 are shown, and the basic configuration will be described.

[0151] The interleaver 100 is a circuit that performs interleaving in five parallel ways by sub-block division. First, a relatively simple case where pruning does not occur (data length K=RC) will be described.

[0152] The interleaver 100 roughly includes: an input switch 101, a memory 102 composed of a plurality of banks (RAM0 to RAM4) that can be independently written and read, an output switch 103, a write block composed of a row counter 105 and a column counter 106. Incoming address generation unit 104, row number calculation unit 107, column number calculation unit 108, output sub-block s...

Embodiment approach 2

[0208] In Embodiment 1, the basic principle that parallel interleaving can be performed without causing contention is shown. In this embodiment, further proposals are (1) simplification of write processing, (2) simplification of read processing, (3) change of sub-block size determination method, (4) structure capable of supporting fewer sub-blocks, and method.

[0209] Fig. 31 shows the structure of the interleaver of this embodiment. Interleaver 200 in FIG. 31 has a circuit configuration capable of realizing the above (1) to (3). Furthermore, the interleaver 200 has a simplified circuit configuration compared to the interleaver 100 of the first embodiment.

[0210] The interleaver 200 generally includes: a memory 201 composed of a plurality of memory banks (RAM0-RAM4) that can be written and read independently, an output switch 202, a write address generation unit 203 composed of a column counter 204, and a column number Calculation unit 205 , row number calculation unit 2...

Embodiment approach 3

[0243] It is particularly effective when the parallel interleaver described in Embodiments 1 and 2 is applied to a turbo decoder. In this embodiment, a configuration in which the parallel interleaver of Embodiments 1 and 2 are integrated into a turbo decoder will be described.

[0244] Fig. 40 shows an outline of a conventionally known turbo decoder. As shown by the part surrounded by a dotted line, its major feature is that an external value (or external information, prior information, etc.) is passed between two SISO decoders (Soft-In Soft-Out decoders). information and repeat processing. This is described in detail in "Berrou, C.; Glavieux, A.; Thitimajshima, P.; "Near Shannon limiterror-correcting coding and decoding: Turbo-codes", IEEE International Conference on Communications, 1993, Pages: 1064-1070 vol.2 "Wait.

[0245] In recent years, in order to realize high-speed communication, high-speed processing is also required for turbo decoders. As a method of increasing...

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Abstract

Provided is a parallel interleaver capable of flexibly responding to changes in an interleaving pattern with a relatively simple structure and preventing memory access contention. It is provided with: constituted by a plurality of memory banks (RAM0~RAM4), each bank corresponds to one or more row numbers arranged two-dimensionally (702); generate other rows respectively in the data structure arranged two-dimensionally A pattern generating unit (710) for rearranging patterns in a plurality of rows specified in ; and a readout control unit (706-712) having a pattern generating unit (710) inside and generating a plurality of addresses based on rearranging patterns in a plurality of rows , reading multiple data from the memory (702) at the same time.

Description

technical field [0001] In particular, the present invention relates to a parallel interleaver, a parallel deinterleaver and an interleaving method, which are used to implement data writing in a row direction-first manner for a two-dimensionally arranged data structure, rearrange each row within a row, and align each row with each other. Rearrange, and read out the interleaving algorithm of the data in a column-first manner. Background technique [0002] (algorithm for interleaving) [0003] First, an algorithm of a conventional interleaver will be described. Interleaving refers to rearranging the data string {d[0], d[1], ..., d[K-1]} of length K, and outputting the data string {d'[0], d'[ 1], ..., d'[K-1]} processing. Each data d[i] can be a single bit or a fixed number of decimal points (so-called soft decision values), and is therefore called a symbol hereinafter. [0004] Among conventional interleaving algorithms, there is an interleaving algorithm using a two-dimens...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/27G06F12/02G06F12/06H04L1/00
CPCH04L1/0066H03M13/2957G06F12/0607H04L1/0071H03M13/276G06F12/0207H03M13/2796H03M13/2771G06F12/02G06F12/06
Inventor 本塚裕幸
Owner PANASONIC CORP