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Dedicated mechanism for page mapping in a gpu

A page table and graphics-based technology, applied in memory address/allocation/relocation, instrument, image memory management, etc., can solve problems such as slowing down the reading and display data rate, and inability to access the second memory

Active Publication Date: 2008-02-06
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, the first memory access precedes the second memory access in tandem, since the second memory access cannot be made without the address provided by the first memory access
Additional first memory accesses may be as long as 1usec, greatly slowing down the rate at which display data or other required data is read

Method used

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  • Dedicated mechanism for page mapping in a gpu
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  • Dedicated mechanism for page mapping in a gpu

Examples

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Embodiment Construction

[0025] Figure 1 is a block diagram of a computing system improved by incorporating an embodiment of the present invention. This block diagram includes central processing unit (CPU) or host processor 100, system platform processor (SPP) 110, system memory 120, graphics processing unit (GPU) 130, media communications processor (MCP) 150, network 160, and internal and peripheral devices 270 . Frame buffer, local or graphics memory 140 is also included, but shown with dashed lines. The dashed line indicates that although conventional computer systems include this memory, embodiments of the present invention allow it to be removed. This figure, like the others included, is shown for illustrative purposes only and does not limit the possible embodiments or claims of the invention.

[0026] CPU 100 is connected to SPP 110 via host bus 105 . SPP 110 communicates with graphics processing unit 130 via PCIE bus 135 . SPP 110 reads data from and writes data to system memory 120 via me...

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PUM

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Abstract

Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system memory. Translation information is maintained by locking or restricting entries in the graphics TLB that are needed for display access. This may be done by limiting access to certain locations in the graphics TLB, by storing flags or other identifying information in the graphics TLB, or by other appropriate methods. In another example, memory space is allocated by a system BIOS for a GPU, which stores a base address and address range. Virtual addresses in the address range are translated by adding them to the base address.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Tong et al., U.S. Provisional Application Nos. 60 / 820,952, filed July 31, 2006, and U.S. Provisional Application Nos. 60 / 821,127, filed August 1, 2006, both titled BOTH "DEDICATED MECHANISM FOR PAGE-MAPPING INA GPU," both of which are incorporated herein by reference. [0003] This application is related to the following commonly owned and co-pending U.S. patent applications: Serial No. 11 / 253,438, filed October 18, 2005, entitled "Zero Frame Buffer"; / 077,662, entitled "Memory Management for Virtual Address Space with Translation Units of Variable Range Size"; and 11 / 077662, filed March 10, 2005, entitled "Memory Management for Virtual Address Space with Translation Units of Variable Range Size Size", said patent applications are incorporated herein by reference. technical field [0004] The present invention relates to eliminating or reducing system memory accesses for retrieving ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T1/60G06F12/10G06F12/1009G06F12/1027
Inventor 彼得·C·童桑尼·S·杨凯文·J·克兰楚施加里·D·洛伦森凯曼·吴阿希什·K·考尔科林恩·S·凯斯斯特凡·A·戈特沙尔克丹尼斯·K·马
Owner NVIDIA CORP