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Semiconductor unit array, and static random access memory array

A memory cell array, static random access technology, applied in static memory, semiconductor/solid-state device components, semiconductor devices, etc., can solve problems such as limiting the performance of traditional SRAM

Active Publication Date: 2010-05-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

They are conflicting goals and limit the performance of traditional SRAM

Method used

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  • Semiconductor unit array, and static random access memory array
  • Semiconductor unit array, and static random access memory array
  • Semiconductor unit array, and static random access memory array

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0057] figure 1 A conventional 6-transistor (6T) SRAM cell 100 is shown. The PMOS pull-up transistor 110 and the NMOS pull-down transistor 115 are at the positive voltage source V dd vs. ground voltage V ss are coupled to form a first inverter. The second inverter is formed by coupling another PMOS transistor 120 and NMOS transistor 125 like the first inverter. Then two inverters are cross-coupled, that is, the output terminal of the first inverter is coupled to the input terminal of the second inverter, and the input terminal of the first inverter is coupled to the output terminal of the second inverter , thereby forming a latch with a bistable state for use as a memory element. Nodes C and D are two storage nodes.

[0058] refer to figure 1 , when node C has a high voltage, the PMOS pull-up transistor 120 will not conduct, but the NMOS pull-down transistor 125 will conduct, thus pulling the voltage of node D to V ss . When node D has a low voltage, NMOS pull-down tra...

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PUM

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Abstract

A semiconductor transistor array is disclosed having a plurality of identical transistors, with sources of the transistors commonly coupled to a first voltage supply, and bulks of the transistors commonly coupled to a second voltage supply which is different from the first voltage supply, wherein different voltages can be supplied to the sources and bulks.

Description

technical field [0001] The invention relates to a semiconductor memory device, in particular to a static random access memory (SRAM) cell array structure. Background technique [0002] Static random access memory (SRAM) has long been the main product of memory due to its characteristics of simple operation, fast access speed, and low power consumption. The simple operation of SRAM comes from the bistable cell, that is, as long as the appropriate voltage is provided, SRAM can maintain its state indefinitely, unlike dynamic random access memory (DRAM), which is generally updated. [0003] A known conventional SRAM cell structure has six transistors (6T) constructed with a pair of pass-gate transistors and two cross-coupled inverters. "Cross-coupled" herein means that the output of an inverter is coupled to the input of another inverter, thus forming a latch circuit with a bistable state. Each inverter is composed of a pull-down NMOS transistor and a pull-up PMOS transistor. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/412H01L27/105H01L27/11H01L23/522
CPCG11C11/413G11C5/14H01L2924/0002H01L2924/00
Inventor 廖忠志
Owner TAIWAN SEMICON MFG CO LTD