High voltage pmos transistor

Abstract

The invention relates to a high-voltage PMOS transistor comprising an insulated gate electrode (18), a p-type source (15) in an n-type well (11), a p-type drain (14) in a p-type well (12), which is located in the n-type well, and a field oxide region (13) between the gate electrode and drain. The depth (A'-B') of the n-type well below the drain (14) is less than its depth below the source (15) and the greatest depth (A'-C') of the p-type well lies below the drain (14).

Description

technical field [0001] The invention relates to a high-voltage PMOS transistor, which has an insulated gate electrode, a p-type conduction source region in an n-type conduction well, and a p-type conduction drain region in a p-type conduction well, the p-type conduction well being arranged in the n-well middle. Background technique [0002] In integrated circuits, the known fabrication of high-voltage transistors generally results in transistors optimized for the desired voltage range. The voltage range can be from greater than 10 volts up to 150 volts and beyond. A typical application is automotive technology, where, in addition to logic circuit elements, switches for the battery voltage level and for controlling disturbance bursts must also be provided. These high-voltage transistors can basically be manufactured by processes as applied to CMOS circuits having a usage range of 3.3 volts or 5 volts. However, this production is complex and expensive, since a number of add...

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Problems solved by technology

However, this document proposes that the withstand voltage strength of the transistor is limited because the retrograde implantations profile in the edge region of the drain extension leads to a less suitable doping pattern

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