Improved Booth2 multiplier structure

Abstract

The utility model relates to an improved Booth 2 multiplier structure, which comprises two partial products realized by hardware and an adder for adding the two partial products; wherein, a bit adding circuit is respectively added on the highest two bits of the two partial product circuits; all partial product bits of the adder are made into same length, at the same time, the number of the partial products does not increase. The utility model has the advantages of small circuit area, simple and regular structure and small influence on the circuit performance.

Description

technical field [0001] The present invention relates to an improved Booth 2 multiplier structure. Background technique [0002] The Booth algorithm is for the two's complement data format, and is mainly responsible for generating partial products during the multiplication operation. The core of the Booth algorithm is the Booth coded partial product generation form of two's complement data. For example, consider an N-bit two's complement number A=(a N-1 , a N-2 ,...,a 0 ), its Booth encoding form is as follows: [0003] A=-a N-1 ·2 N-1 +∑a i ·2 i =∑(a i-1 -a i )2 i (1) [0004] where (i=0,1,...,N-1); a -1 =0 [0005] so: [0006] P=A×B=∑(a i-1 -a i )×B×2 i (2) [0007] The above formula is Booth 1-order coding, and the actual Booth 1 coding table and the corresponding partial product operation can be obtained through the formula, as shown in Table 1. [0008] Table 1 1st order Booth coding table [0009] a i a i-1 Booth coding...

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Problems solved by technology

Therefore, the existing design has the disadvantages that partial product circuits cannot be reused, or the number of partial products needs to be increased, resulting in large consumption of circuit area, complex structure and irregular circuits.

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