A method and system for reducing transmission clock line based on communication hardware platform

Abstract

The invention discloses a method for reducing a clock-transmission line based on a communication hardware platform. The method includes the following steps: A. a sending end of a system clock modulates the system clock signals of various types into the serial data signals in an encoding way, and transmits the serial data signals via the clock bus to a receiving end of the system clock on each interface unit board; B. the receiving end of the system clock decodes the serial data signals and recovers the system clock signals. The invention transmits a plurality of clock signals only by using a few lines, meeting the system demand for the adaptability and enhancing the reliability of the system.

Description

technical field [0001] The invention relates to the field of computers, in particular to a method for transmitting and receiving a clock signal in a computer communication hardware platform and a system thereof. Background technique [0002] The system clock signal in the communication hardware platform generally includes: 8K frame signal, 16.384M clock signal; sometimes it is added according to business needs: PP2S synchronization signal, period 1.25ms clock signal, 19.44M clock signal, etc. The traditional system clock transmission method is to use independent signal lines to transmit various clock signals. With the advancement of technology, the requirements for system integration and reliability are getting higher and higher, and the shortcomings are becoming more and more obvious: [0003] (1) The internal backplane of the system module requires many connections. In the current communication hardware platform, the number of backplane connections used to transmit system ...

AI Technical Summary

Problems solved by technology

[0003] (1) The internal backplane of the system module requires many connections. In the current communication hardware platform, the number of backplane connections used to transmit system clock signals according to the standard is only three groups, and this method cannot transmit all clocks. signal, which will affect the business application range of the system

[0004] (2) The number of clock cables required to transmit clock signals between system modules is large

If the clock cable is directly connected to transmit the clock signal between modules, there is a danger of surge damage to the interface chip

[0006] (4) The traditional clock transmission method has poor scalability because each clock signal occupies a clock channel, and it is not suitable for the increase in the types of clock signals in the future.

However, in current and future systems, due to the improvement of integration, the connections allocated to the system clock signal will not be as abundant as before, and more clock signals will be added as needed, so the requirements for system reliability and adaptability The requirements are getting higher and higher, so it can be seen that the existing system needs a new method to transmit clock signals, which requires the transmission of clock signals required by various systems on a limited clock line, and meets the reliability requirements of the system

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