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Switch matrix system with plural bus arbitrations per cycle via higher-frequency arbiter

An arbiter and bus technology, applied in the field of high-performance bus arbitration system, can solve the problems of chip area consumption, routing complexity, increased power consumption, etc.

Inactive Publication Date: 2008-04-09
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, implementing many arbiters consumes chip area, complicates routing, and increases power consumption

Method used

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  • Switch matrix system with plural bus arbitrations per cycle via higher-frequency arbiter
  • Switch matrix system with plural bus arbitrations per cycle via higher-frequency arbiter
  • Switch matrix system with plural bus arbitrations per cycle via higher-frequency arbiter

Examples

Experimental program
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Embodiment Construction

[0014] FIG. 3 depicts a timing diagram for a representative bus transaction request and arbitration in a crossbar matrix system 30 . In this example, the bus operates at a bus frequency of 100 MHz with a clock cycle of 10 ns, and two slaves A and B share a single arbiter. Both slaves M0 , M1 simultaneously issue requests for bus transactions directed to the two slaves A and B in bus cycle 1 .

[0015] In a system 30 with a conventional arbiter, slave A would be arbitrated in bus cycle 2 and slave B would be arbitrated in bus cycle 3 as indicated by the dashed lines. The arbiter will issue a request to slave A in bus cycle 3 and a request to slave B in bus cycle 4 as indicated by the dotted lines. The slaves will acknowledge in bus cycles 4 and 5, respectively, and masters MO and Ml can proceed with the bus transaction upon receipt of each respective slave acknowledgment.

[0016] In one or more embodiments, by operating the arbitrator at an arbiter frequency greater than the...

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Abstract

An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with one instance of arbitration logic. The arbiter may arbitrate for two or more slave devices, or may arbitrate multiple master device requests directed to the same slave device. The arbiter frequency may be variable, and may be predicted based on, e.g., prior bus activity. If only one bus transaction request is pending, the arbiter frequency may equal the bus frequency. The results of an earlier arbitration decision may be utilized to more intelligently make subsequent arbitration decisions in the same bus frequency clock cycle.

Description

technical field [0001] The present invention relates generally to the field of electronic data processing and, in particular, to a high performance bus arbitration system and method. Background technique [0002] Data transfer between functional units is a common operation of computer systems. Transferring programs from disk to memory to the processor, sending data from the graphics engine to the frame buffer to the video card, and sending input from the keyboard or mouse to the processor are all common examples of data transfer within a computer system . [0003] FIG. 1 depicts a simplified diagram of a system bus structure, generally indicated by the numeral 10 . The system bus 12 interconnects various system units, and the system bus 12 can be divided into address channels, data channels, control channels and the like. A master device, such as CPU 14 or DMA engine 16, instructs a data transfer across bus 12—referred to herein as a bus transaction—to or from a slave dev...

Claims

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Application Information

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IPC IPC(8): G06F13/40
CPCG06F13/4022H04L49/101Y02D10/00G06F13/40
Inventor 贾亚·普拉喀什·苏布拉马尼亚姆·贾纳桑
Owner QUALCOMM INC