Time sequence improving circuit

Abstract

The invention relates to a sequential improvement circuit, which comprises a control circuit and a switching circuit, wherein, the control circuit comprises a first switch element and a second switch element; the input end of the first switch element is connected with a node; the voltage of the node is on a high electric level under startup condition and on a low electric level under shutdown and standby conditions; the output end of the first switch element is connected with a control signal terminal outputted by a chip set and the input end of the second switch element; the output end of the second switch element is connected with an input / output control chip; the input end of the switching circuit is connected with the node while the output end is connected with the input / output control chip to output the input / output control chip with a signal which is in the high electric level under startup condition and the low electric level under shutdown and standby conditions. The sequential improvement circuit can make the timing sequence of the control signal for controlling computer standby condition outputted by the chip set consistent with the timing sequence of the signal for controlling computer standby condition in the input / output control chip, so a normal operation of a computer can be ensured.

Description

technical field [0001] The invention relates to a timing improvement circuit, in particular to a timing improvement circuit which can make the timing of the signal output by the chipset on the motherboard to control the sleep state of the computer consistent with the timing of the signal controlling the sleep state in the input and output control chip. Background technique [0002] The chipset is an important part of the motherboard and affects almost all functions of the motherboard. When the computer enters the dormant state, it is required that the timing of the signal controlling the dormant state output by the chipset is consistent with the timing of the signal controlling the dormant state in the input and output control chips. Different, it is inevitable that the signal timing of the chipset on the motherboard is not compatible with the signal timing of the input and output control chips, which will affect the normal operation of the computer. Contents of the invent...

AI Technical Summary

Problems solved by technology

When the computer enters the dormant state, it is required that the timing of the signal controlling the dormant state output by the chipset is consistent with the timing of the signal controlling the dormant state in the input and output control chips. Different, it is inevitable that the signal timing of the chipset on the motherboard is not compatible with the signal timing of the input and output control chips, which will affect the normal operation of the computer.

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