Handling cache miss in an instruction crossing a cache line boundary

Abstract

A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.

Description

technical field [0001] The present subject matter relates to efficiently handling the fetching of an instruction that crosses a cache line boundary, especially if a second portion of the instruction is not already in the cache from which the processor attempted to fetch the instruction (cache miss). Background technique [0002] Modern microprocessors and other programmable processor circuits utilize memory hierarchies to store and serve instructions. Common levels include the instruction cache, or L1 cache, relatively close to the core of the processor, eg, on the processor chip. Instructions are loaded from a slightly distant or L2 cache, which stores both instructions and data, into the L1 instruction cache. One or both cache memories are loaded with instructions from main memory, and the main memory may be loaded from a more distant source, such as a disk drive of the device incorporating the processor. Cache memory improves performance. Fetching instructions from, fo...

AI Technical Summary

Problems solved by technology

However, such solutions add complexity in the construction of the fetch stage, in its interconnection w

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