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System and method for controlling etching deviation

An etching and deviation technology, applied in the field of systems for controlling etching deviation, can solve problems such as low production efficiency, and achieve the effect of improving production efficiency and saving production costs

Inactive Publication Date: 2008-10-08
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Adjust the value of ADI CD according to the etching deviation produced by the test wafer. Obviously, this method usually requires many experiments to determine an appropriate value of ADI CD, and the production efficiency is very low.

Method used

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  • System and method for controlling etching deviation

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Embodiment Construction

[0010] see figure 1 After the etching process is completed, a layer of metal dielectric layer 3 covered on the wafer 1 is covered with a layer of photoresist 5 on the metal dielectric layer 3 .

[0011] The present invention utilizes the relationship between etching bias (Etch bias) and mask transmission rate (Mask transmission rate) and the etching bias is the difference between AEI CD and ADI CD. Among them, ADI CD (Critical Dimension) is the size of a specific pattern after photolithography development, and AEI CD is the size of the dielectric layer after etching. In the embodiment of the present invention, the 0.13 μm process is taken as an example, but the present invention is also applicable to other processes.

[0012] Please refer to Table 1, which lists the relationship between the etching deviation and the mask transmission rate (Mask transmission rate) is basically linear. In this case, assuming that the target value of AEI CD required by the process is 0.2 μm, th...

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PUM

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Abstract

The invention provides a system for controlling etching deviation, which includes a manufacturing engineering system for accurately controlling whole pattern manufacture process size and a light mask data system for connecting with the manufacturing engineering system. The light mask data system is used for obtaining light mask light transmittance and transmitting the obtained light transmittance data to the manufacturing engineering system. The manufacturing engineering system can automatically identify range of the light mask light transmittance and calculate optimal size of photoetching manufacturing process. The invention also provides a method for controlling the etching deviation. By utilizing line-type corresponding relationship of the light mask light transmittance and the etching deviation, the manufacturing engineering system can obtain the corresponding etching deviation by obtaining the light mask light transmittance from thelight mask data system, thereby calculating the optimal size of photoetching manufacturing process; by utilizing connection and feedback of the manufacturing engineering system and the light mask data system, final size of the whole pattern manufacture process can be accurately controlled, thereby effectively increasing production efficiency and saving production cost.

Description

technical field [0001] The invention relates to semiconductor etching process, in particular to a system and method for controlling etching deviation. Background technique [0002] ADI CD (Critical Dimension) is the size of a specific pattern after photolithography development, and AEI CD is the size of the dielectric layer after etching. Etch bias is the etching bias, which is obtained from the difference between AEI CD and ADI CD. In an actual etching process, etching deviation is an important parameter affecting etching. [0003] When a factory produces a new product, it is usually impossible to estimate the exact ADI CD value in advance to obtain the required AEI CD value. In order to control the AEI CD within a predetermined range, the ADI CD value is usually estimated in advance based on empirical values. Test wafers are used for pre-production. Adjust the value of ADI CD according to the etching deviation produced by the test wafer. Obviously, this method usually r...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/311H01L21/66H01L21/00
Inventor 曾坤赐
Owner SEMICON MFG INT (SHANGHAI) CORP