Method for measuring MOS transistor dismatching features, territory pattern and forming method thereof

Abstract

A method for measuring MOS transistor mismatch characteristic includes steps: generating at least one group of first edition patterns containing two or more same MOS transistors; generating at least one group of second edition patterns which have same pattern with the first edition pattern but have different arrangement angle with the first edition pattern; transferring the first edition patterns and the second edition patterns on a semiconductor chip and generating at least two groups of semiconductor devices having different arrangement angle on the semiconductor chip; measuring electric parameter of the MOS transistors in the semiconductor device; calculating difference of electric parameter for the MOS transistors having same structure and preparation technique in each group of semiconductor device; calculating standard deviation of the difference for the semiconductor devices having same arrangement angle and comparing the standard deviation of the semiconductor devices having different arrangement angle. The invention also provides a edition pattern and forming method thereof. The measuring method of present invention can truly and all sidedly reflect mismatch characteristic of same MOS transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing and testing, in particular to a method for measuring mismatch characteristics of two or more identical metal oxide semiconductor transistors in a semiconductor device, a layout pattern and a forming method thereof. Background technique [0002] Metal-oxide-semiconductor transistors (Metal-Oxide-Semiconductor, MOS) have the advantages of low power consumption and fast response speed, and are widely used in the fields of computers, communications and storage. In some circuits using MOS transistors, two or more identical MOS transistors are often used. For example, a static random access memory (Static Random Access Memory, SRAM) storage unit. US Patent No. US 5744844 discloses a Static Random Access Memory (SRAM) storage unit composed of six MOS transistors. figure 1 It is a circuit diagram of the SRAM memory cell disclosed in the said US patent. Such as figure 1 As shown in ...

AI Technical Summary

Problems solved by technology

However, the method of obtaining the mismatch characteristics of the same MOS transistor by computer simulation is realized based on building a model. The process of building a model is an approximate description of the real situation, and cannot fully and truly reflect the mismatch characteristics of the product.

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