Detection Structure and Method for Mismatch Characteristics of Semiconductor Devices

Abstract

Disclosed are a detection structure and a detection method of a semiconductor device mismatch characteristic. The detection structure of the semiconductor device mismatch characteristic comprises a semiconductor substrate, a plurality of identical semiconductor devices which are located on the surface of the semiconductor substrate and at least one circular ring which is surrounded by the semiconductor devices in an equal angle mode. In the detection structure of the semiconductor device mismatch characteristic, the semiconductor devices have different laying angles, by comparing the difference value or the standard deviation of the semiconductor devices with the different laying angles, the influence of the different laying angles on a semiconductor silicon wafer on the mismatch characteristic of the semiconductor devices is judged, and thereby the influence of manufacturing technique and semiconductor chips on the electrical parameter mismatch of the semiconductor devices are obtained, great help about the best locating place of the semiconductor devices is offered for designers in the designing process of an integrated circuit board, and moreover, reference is offered for reducing the mismatch characteristic of a metal oxide semiconductor (MOS) transistor caused in the manufacturing process.

Description

technical field

[0001] The invention relates to semiconductor test technology, in particular to a detection structure and a detection method for detecting mismatch characteristics of a plurality of identical semiconductor devices. Background technique

[0002] With the continuous development of integrated circuit technology, the number of semiconductor devices integrated in a single chip is increasing. When designing an integrated circuit, it is usually necessary to use several semiconductor devices with the same electrical parameters. For example, when designing a storage unit of a Static Random Access Memory (SRAM), several MOS transistors with the same electrical parameters are required. The US patent No. US5744844 discloses a SRAM composed of 6 MOS transistors. Please refer to figure 1 , is the circuit diagram of the SRAM storage unit disclosed in the US patent, the SRAM storage unit has four NMOS transistors 11, 12, 13, 14 and two PMOS transistors 15, 16, when carryin...

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