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Data processing method and communications system and relevant equipment

A technology of processor and target device, applied in the field of communication

Active Publication Date: 2011-11-02
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in the NTB system architecture of the prior art, the devices on both sides of the NTB have independent addressing spaces, and the addressing spaces on both sides may overlap. After the IO device issues a DMA command for the second IO device to access the first memory, since the DMA address information carried in the DMA command is for the addressing space of the first CPU side, when the second IO device on the other side of the NTB After the device receives the DMA command, it will access the second memory in the address space of the local side according to the DMA address information, instead of accessing the first memory on the first CPU side. Therefore, in the existing NTB system, the IO device cannot use multiple DMA command issued by CPU for DMA access

Method used

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  • Data processing method and communications system and relevant equipment
  • Data processing method and communications system and relevant equipment
  • Data processing method and communications system and relevant equipment

Examples

Experimental program
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Effect test

Embodiment 1

[0034] Such as image 3 As shown, the data processing method of this embodiment includes the following steps:

[0035] 301. The first IO device on the first side of the NTB receives a DMA command sent by the CPU, and the DMA command carries a memory address; the CPU may be the second CPU on the second side of the NTB or the first CPU on the first side of the NTB, and the memory It can be the second memory on the second side of the NTB or the first memory on the first side of the NTB; where the first IO device, the first CPU, and the first memory are on the first side of the NTB, using the same first addressing space ; The second CPU and the second memory are on the second side of the NTB, using the same second addressing space; the first addressing space and the second addressing space are mutually independent addressing spaces; the first CPU and the second The CPU will allocate an address space to NTB for the mutual mapping of the two address spaces, and establish the corres...

Embodiment 2

[0043] see Figure 4 , the data processing method of this embodiment includes:

[0044] 401. The CPU on the source side constructs a DMA command and sends it to the target device. When the target device and the CPU are on the same side of the NTB, the CPU directly sends the DMA command to the target device on the same side through the bus. When the target device and the CPU are on the same side of the NTB When the different sides of the CPU are on different sides, the CPU forwards the DMA command to the target device on the other side through the NTB;

[0045] Wherein, the DMA command includes a source side address of the target device and a DMA source side address, the source side address of the target device is used to indicate the receiving device of the DMA command, and the DMA source side address is used to indicate the memory during the DMA operation;

[0046] In this embodiment, when the first CPU needs to communicate with the second IO device isolated by the NTB, the ...

Embodiment 3

[0067] see Figure 5 , the data processing method of this embodiment includes:

[0068]501. The CPU on the source side constructs a DMA command and sends it to the target device. When the target device and the CPU are on the same side of the NTB, the CPU directly sends the DMA command to the target device on the same side through the bus. When the target device and the CPU are on the same side of the NTB When the different sides of the CPU are on different sides, the CPU forwards the DMA command to the target device on the other side through the NTB;

[0069] Wherein, the DMA command includes a source side address of the target device and a DMA target side address, the source side address of the target device is used to indicate the receiving device of the DMA command, and the DMA target side address is used to indicate the memory during the DMA operation;

[0070] In this embodiment, when the first CPU needs to communicate with the second IO device isolated by the NTB, the f...

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Abstract

The embodiment of the invention discloses a data processing method, a communication system and relevant equipment. The invention is used to realize the DMA access of IO equipment on the basis of multi-CPU. The method of the embodiment comprises the following steps that: a direct memory access DMA command is received, wherein, the DMA command comprises a DMA address of a memory for indicating the DMA operation access; according to the DMA command, a DMA address indicated by an address space of a receiver is acquired; according to the acquired DMA address indicated by the address space of the receiver, the memory is accessed. The embodiment of the invention also discloses the communication system and the relevant equipment. The embodiment of the invention can realize the DMA access of the IO equipment on the basis of the multi-CPU.

Description

technical field [0001] The invention relates to the field of communication, in particular to a data processing method, a communication system and related equipment. Background technique [0002] The central processing unit (CPU, Center Processing Unit) communicates with the input-output (IO, Input-Output) device through the peripheral device expansion interface (PCIE, Peripheral Component Interconnect Express) bus, and the main addressing mode of PCIE is based on address addressing . If there are two or more processors in the PCIE bus, the address spaces between these processors may overlap. At this time, if the original address is still addressed in the PCIE bus, address conflicts will inevitably occur. [0003] For the above problems, the prior art proposes a solution: when there are multiple processors in the PCIE bus, use a non-transparent bridge (NTB, Non-Transparent Bridge) to isolate, and the non-transparent bridge isolates the PCIE devices on both sides of the bridg...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/28
Inventor 麦嘉源
Owner HUAWEI TECH CO LTD
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