Multiplication digital-analog conversion circuit
A digital-to-analog conversion and circuit technology, applied in the direction of digital-to-analog converters, etc., can solve the problems of low requirements for establishment accuracy, large margins, waste of establishment phase power consumption, etc., and achieve the requirements of lower requirements, lower power consumption, and balanced establishment. Effect
Active Publication Date: 2010-08-25
中科芯未来微电子科技成都有限公司
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Problems solved by technology
In the op-amp sharing circuit, the two-stage MDAC circuit uses the same op-amp. Since the feedback capacitance and load capacitance of the first-stage MDAC are large, the shared op-amp must satisfy the establishment of the first-stage MDAC. In this way, in the When the two-stage MDAC is established, the margin for the establishment of the operational amplifier is relatively large, and the requirements for the establishment accuracy of the second stage are lower than those of the first stage. The clock scheme shown in Figure 4 is adopted. Since the two-phase time is basically equal, the second stage There will be a certain waste of power consumption during the establishment of the stage
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[0031] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0032] As shown in FIG. 5 , FIG. 5 is a schematic structural diagram of an operational amplifier sharing MDAC circuit of a two-phase non-overlapping clock scheme provided by the present invention. The operational amplifier shared MDAC includes a first-stage MDAC circuit and a second-stage MDAC circuit. Wherein, the first-stage MDAC circuit is used for performing residual amplification on the differential signals in1 and in2 received from the outside, and outputting the obtained differential signals out1_1 and out2_1 to the second-stage MDAC. The second-stage MDAC circuit is used to perform residual amplification on the differential signals out1_1 and out2_1 received from the first-stage MDAC, and output the obtained diffe...
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The invention relates to the technical field of digital signal processing and discloses a multiplication digital-analog conversion circuit shared by operational amplifiers which adopt a two-phase unbalance clock proposal. The multiplication digital-analog conversion circuit comprises a first-stage MDAC (multiplication digital-analog conversion) circuit and a second-stage MDAC circuit which adopt the same effective digits and redundant digits; the sampling capacitance and the feedback capacitance in the second-stage MDAC circuit are lower than the sampling capacitance and the feedback capacitance in the first-stage MDAC circuit while the residual amplification phase time in the first-stage MDAC circuit is longer than that of the second-stage MDAC circuit. The invention also discloses a pipeline analog-to-digital converter (ADC) which utilizes an MDAC circuit shared by the operational amplifiers which adopt the two-phase unbalance clock proposal. By utilizing invention, the power consumption of the operational amplifier on each phase is fully utilized and the waste of the power consumption is reduced.
Description
technical field [0001] The present invention relates to the technical field of digital signal processing, in particular to a multiplication digital-to-analog conversion circuit (Multiplying Digital to Analog Circuit, MDAC), and a low-power pipeline analog-to-digital converter (Analog to Digital Circuit, ADC) applying the MDAC circuit ). Background technique [0002] At present, with the wide application of digital signal processing technology in the field of communication, the demand for medium-precision, high-speed analog-to-digital converters in high-speed modems, broadband wired and wireless communication systems is increasing. Among ADCs of various structures, the pipeline ADC is widely used because of its unique trade-off advantages in terms of speed, power consumption and area. [0003] As shown in FIG. 1 , FIG. 1 is a schematic structural diagram of a traditional pipeline ADC. It consists of a front-end sample-and-hold circuit, several sub-stages (STAGE1, STAGE2, .....
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IPC IPC(8): H03M1/66
Inventor 郑晓燕周玉梅
Owner 中科芯未来微电子科技成都有限公司