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Circuit and method for self repairing multiport memory

A technology for repairing circuits and repairing methods, applied in static memory, instruments, etc., can solve problems such as multi-port memory port related errors, no reliable self-repair technology, etc., to avoid incorrect or incomplete repairs.

Inactive Publication Date: 2008-11-12
FARADAY TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In summary, there are currently no reliable self-healing techniques for port-related errors in multi-ported memories

Method used

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  • Circuit and method for self repairing multiport memory
  • Circuit and method for self repairing multiport memory
  • Circuit and method for self repairing multiport memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0046] Please refer to the following instructions image 3 and Figure 4 . image 3 is a schematic diagram of a multi-port memory self-healing circuit 300 according to an embodiment of the present invention, Figure 4 It is a flow chart of the multi-port memory self-healing method executed by the self-healing circuit 300 . The multi-port memory self-repair circuit 300 includes a test analysis module 302 and a defect location module 303 , and the test analysis module 302 further includes a self-tester 304 and a backup component analyzer 305 . The repairable multi-port memory 301 , the self-tester 304 , the backup component analyzer 305 , and the defect location module 303 are coupled to each other.

[0047] Figure 4 The process starts from step 405. The self-tester 304 tests the repairable multi-port memory 301 to generate an error location at step 405 . In step 410, the backup component analyzer 305 judges whether the above-mentioned test generates a port-related error ...

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PUM

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Abstract

The invention discloses a self-repair circuit of a multiport memory and a corresponding method thereof. The self-repair circuit comprises a test analysis module and a flaw-positioning module; wherein the flaw-positioning module is coupled with the test analysis module. The test analysis module tests a repairable multiport memory in order to generate a wrong position and judges whether the test causes relevant port errors according to the wrong position. If the test causes the relevant port errors, the flaw-positioning module generates a flaw position according to the wrong position and provides the flaw position to the test analysis module which decides how to repair the repairable multiport memory according to the flaw position; otherwise, if the test does not cause the relevant port errors, the test analysis module decides how to repair the repairable multiport memory according to the flaw position.

Description

technical field [0001] The invention relates to a memory self-repair circuit and method, in particular to a multi-port memory (multi-port memory) self-repair circuit and method. Background technique [0002] Testing becomes a big problem when circuits on a chip contain multiple memories. If an external device is used for testing, the input and output terminals of all memories must be connected to the outside of the chip. Such a large number of lines not only occupies the chip area, but also increases the difficulty of circuit layout. practical. So someone proposed the concept of self-test (BIST: built-in self test), that is, to manufacture the test circuit and the memory under test on the same chip, so that it is not necessary to connect the input and output terminals of all memory to the chip off. After the repairable memory (repairable memory) came out, the self-test technology was extended to a self-repair technology (BISR: built-in self repair). [0003] Traditional ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/44
Inventor 曾子维黄瑜真吴俊贤李进福包建元
Owner FARADAY TECH CORP
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