Method and system for performing independent loading for reinforcement processing unit

A processing unit and enhanced processing technology, applied in the direction of concurrent instruction execution, machine execution device, electrical digital data processing, etc., can solve the problem of convenience without supporting out-of-order execution scenarios

Inactive Publication Date: 2008-12-17
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Without the convenience of supporting all out-of-order execution scenarios, it may not be possible to change the ordering of instructions so that forward progress through the instruction stream can be performed while retrieving missing data

Method used

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  • Method and system for performing independent loading for reinforcement processing unit
  • Method and system for performing independent loading for reinforcement processing unit
  • Method and system for performing independent loading for reinforcement processing unit

Examples

Experimental program
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Embodiment Construction

[0027] The illustrative embodiments provide a prefetch assistance mechanism to enhance the execution of independent loads in a single-thread assistance mode. Utilizing the illustrative embodiments, a data processing system provides a method of enhancing execution of independent loads in a single-threaded mode. figure 1 is provided as an exemplary data processing system in which aspects of the illustrative embodiments may be implemented. Data processing system 100 is an example of a computer in which computer usable code or instructions implementing the processes for the illustrative embodiments of the invention may be installed.

[0028] In the depicted example, data processing system 100 employs a hub architecture including north bridge and memory controller hub (NB / MCH) 102 and south bridge and input / output (I / O) controller hub (SB / ICH) 104 . Processing unit 106 , main memory 108 and graphics processor 110 are connected to NB / MCH 102 . Graphics processor 110 may be connect...

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Abstract

A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. A processing unit detects if a long-latency miss associated with a load instruction has been encountered. Responsive to a long-latency miss, the processing unit enters a load lookahead mode. Responsive to entering the load lookahead mode, the processing unit dispatches each instruction from a first set of instructions from a first buffer with an associated vector. The processing unit determines if the first set of instructions from the first buffer have completed execution. Responsive to completed execution of the first set of instructions from the first buffer, the processing unit copies the set of vectors from a first vector array to a second vector array. Then the processing unit dispatches a second set of instructions from a second buffer with an associated vector from the second vector array.

Description

technical field [0001] The present application generally relates to improved data processing systems and methods. More specifically, the present application focuses on enhanced load lookahead prefetching in single-threaded mode for simultaneous multi-threaded microprocessors. Background technique [0002] There is a continual demand from computer users to maximize performance, and a corresponding pressure on the computer industry to increase the computing power and efficiency of microprocessors. This is especially evident in the world of server computers, where all businesses rely on their computer infrastructure to perform and monitor day-to-day activities that affect revenue, profits, and the like. Increased microprocessor performance will provide computer users with additional resources while providing computer manufacturers with mechanisms to differentiate themselves from the competition. [0003] In a few years, state-of-the-art microprocessors have evolved from fairl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/30032G06F9/30101G06F9/30105G06F9/3012G06F9/3802G06F9/3851G06F9/3885
Inventor 唐·Q·古延杭·Q·利
Owner INT BUSINESS MASCH CORP
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