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Regulation test system and method of on-chip system as well as on-chip system

A system-on-chip and commissioning technology, applied in the field of system-on-chip, can solve problems such as inability to perform commissioning

Active Publication Date: 2011-08-24
ACTIONS ZHUHAI TECH CO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The invention provides a SOC commissioning system, which can overcome the defect that the commissioning cannot be performed due to errors in JTAG interface-related circuits

Method used

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  • Regulation test system and method of on-chip system as well as on-chip system
  • Regulation test system and method of on-chip system as well as on-chip system
  • Regulation test system and method of on-chip system as well as on-chip system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0097] The external boot memory in this embodiment is NOR flash memory, and the memory interface pins may include read and write data pins and digital logic function pins. Among them, the read and write data pins are a collection of pins with any one or more functions of read function, write function, and data transmission function, and are used as the transmission channel for the commissioning program from the external boot memory to the inside of the system on chip; digital logic Function pins are a collection of pins such as address pins and chip select pins, which are used for the pin multiplexing controller to enable the external boot memory through the digital logic function pins.

[0098] Figure 4 A schematic structural diagram of the commissioning system in this embodiment is shown. see Figure 4 , the commissioning system includes: SOC 40 and non-flash memory 41 as an external boot memory; Select control input pin 404, read / write data pin 405 and digital logic fun...

Embodiment 2

[0118] This embodiment considers that each part of the SOC needs to be verified during the commissioning phase. Therefore, a static random access memory is added inside the SOC to store the commissioning program read from the external boot memory, so as to release the read and write data pins. And the occupancy of the digital logic function pins is convenient for debugging these two pins.

[0119] Image 6 A schematic structural diagram of the commissioning system in this embodiment is shown. see Image 6 , the commissioning system includes: SOC 60 and NOR flash memory 61 as an external boot memory; and, the SOC60 in the figure is in Figure 4 SRAM 607 is added on the basis of .

[0120] The microcontroller 601 in this embodiment is similar to the microcontroller 401 in Embodiment 1, the difference is that the microcontroller 601 in this embodiment also allocates and or non-flash memory for the SRAM 607 through the memory controller different addresses, and obtain the debu...

Embodiment 3

[0143] In this embodiment, adopt such as safe digital storage (SD, Secure Digital Memory) card, NAND flash memory, memory stick (MS, Memory Stick), micro-hard disk and other types of memory as the external boot memory, this time in pin multiplexing control An interface conversion controller is added between the device and the memory interface pins.

[0144] The following is an example of NAND flash memory.

[0145] Figure 8A schematic structural diagram of the commissioning system in this embodiment is shown. see Figure 8 , the commissioning system includes: SOC 80 and NAND flash memory 81 as an external boot memory; and, the SOC80 in this figure includes: microcontroller 801, memory controller 802, pin multiplexing controller 803, interface conversion control device 804, boot memory chip select control input pin 805, and memory interface pin 806.

[0146] The microcontroller 801 in this embodiment is the same as the microcontroller 401 in Embodiment 1. The difference b...

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Abstract

The invention discloses a system-on-chip, a testing method and a testing system of the system-on-chip. The system-on-chip in the invention comprises: a microcontroller, a pin multiplexing controller, a bootstrap memory chip selection control input pin and an interface pin of the memory for connecting an external bootstrap memory which is positioned outside the system-on-chip, wherein, when the level of the pin multiplexing controller on the bootstrap memory chip selection control input pin is the out-chip start level, the external bootstrap memory is enabled through the interface pin of the memory; the microcontroller reads a testing procedure from the external bootstrap memory through the interface pin of the memory after the external bootstrap memory is enabled. The proposal can effectively overcome the shortcoming that the test can not be carried out due to the error of a JTAG interface related circuit.

Description

technical field [0001] The present invention relates to integrated circuit technology, in particular to a commissioning system for commissioning a System-on-a-Chip (SOC, System-on-a-Chip), a system-on-a-chip commissioning method, and a system-on-a-chip. Background technique [0002] SOC, developed based on microcontroller (MCU, Micro-Controller Unit) technology and digital signal processing (DSP, Digital Signal Processing) technology, is a special-purpose integrated circuit chip that contains a complete application The circuits of all required functional units can run corresponding embedded software, so they have all or almost all functions of system-level products. In recent years, due to the excellent management, control and fast data processing capabilities of SOC itself, it has been widely used in the fields of communication, intelligent control, computer and testing, and has become the basis of voice processing and image hardware processing technology. It provides powe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
Inventor 王惠刚
Owner ACTIONS ZHUHAI TECH CO
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