VLSI layout planning centralized constrain implementing method

An implementation method and centralized technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of difficult manual layout, difficulty in meeting various constraints at the same time, etc., to avoid convergence reduction and save the conversion process. Effect

Inactive Publication Date: 2011-04-06
FUDAN UNIV
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AI Technical Summary

Problems solved by technology

However, with the number of module divisions or the number of modules in the SOC and the increase of constraints, the manual layout by engineers based on experience in the past is becoming more and more difficult, and it is difficult to meet various constraints at the same time. Therefore, BBL ( Building Block Layout) layout planning problem has been extensively studied

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  • VLSI layout planning centralized constrain implementing method
  • VLSI layout planning centralized constrain implementing method
  • VLSI layout planning centralized constrain implementing method

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Embodiment Construction

[0045] ①. Read the layout input information, store the area, length, width, type, connection and constraint information of each module;

[0046] ②. Construct the allowable initial layout according to the requirements of centralized constraints: first connect the modules involved in each constraint into subtrees, and divide the modules not involved in constraints into subtrees separately, and then connect the subtrees to form an overall B*-tree. ;

[0047] ③. The simulated annealing algorithm is used to optimize the global factors such as area.

[0048] The basic operations in simulated annealing are rotation, exchange, deletion and insertion. The operation method is: (1) Rotation operation: exchange the length and width of a certain module. (2) When the basic operations of exchange, deletion, and insertion are all performed on internal nodes of the same subtree, that is, when two nodes are exchanged or deleted nodes and inserted nodes are performed in the same subtree, such ...

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Abstract

The invention belongs to a technical field of an integrated circuit computer aided design, in particular to the implementation method of centralized constraint in VLSI layout planning. The method is combined with B<*> -tree representation, simulated annealing algorithm and linear programming algorithm. The steps comprise that a constrained sub-tree is constructed according to constraint, each sub-tree is connected so as to form a permissible initial layout, and the simulated annealing algorithm is adopted to optimize such factors as areas, and the like; the constraint condition of linear programming is obtained from the initial layout, a linear programming matrix is constructed, a linear programming function is called for solving the linear programming matrix, compressing operation and soft module adjustment are carried out, and finally the result of optimizing the layout is obtained. The method is used for realizing the constraint that a plurality of modules need to be centralized and placed in a plane layout, and also is used for realizing the centralized constraint on the basis of a plurality of divisions or a whole division.

Description

technical field [0001] The invention belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to a method for realizing geometric constraints in layout planning, which realizes centralized constraints in layout planning. Background technique [0002] With the continuous expansion of the scale of integrated circuits, the layout of integrated circuits becomes more and more complex, so the research on floorplanning algorithms of integrated circuits has received extensive attention in recent years. Layout is a very critical step in the design of large-scale integrated circuits (VLSI). It has an important impact on the smooth completion of subsequent design work, and to a certain extent determines the size and performance of the chip [1]. With the continuous increase in the scale and complexity of VLSI design, the layout is no longer just to optimize the chip area and the length of the signal connection, but to optimize the geometr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 王琳凯陈珊珊周电周晓方
Owner FUDAN UNIV
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