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Clock management between two endpoints

A clock management and clock technology, which is applied in time division multiplexing systems, digital transmission systems, electrical components, etc., and can solve problems such as large-scale processing and complex technology.

Inactive Publication Date: 2009-02-11
AVAYA TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The technique is complex and requires extensive processing to maintain

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  • Clock management between two endpoints
  • Clock management between two endpoints
  • Clock management between two endpoints

Examples

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Embodiment Construction

[0026] Exemplary embodiments of the present invention relate to clock adjustment. However, it should be understood that in general, the systems and methods of the present invention are equally applicable to any communication system and any environment, can be used for the exchange of any type of data, and can adjust any type of clock.

[0027] The exemplary systems and methods of the present invention are also described with respect to communication systems and associated communication hardware, software, and communication channels and networks. However, in order to avoid unnecessarily obscuring the present invention, well-known structures, network components and devices that may be shown in block diagram form in the following description are known or briefly described.

[0028] For purposes of explanation, several details are set forth in order to assist in a thorough understanding of the invention. However, it should be understood that the invention may be practiced in vari...

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Abstract

The invention relates to clock management between two end points across packet switched networks. Clock correlation can be achieved, for example, utilizing the RTP stream between a sender and receiver by determining a baseline at the start of, for example, a communication. This baseline is derived as a point in time from an arriving packet and represents a point from which subsequent packets deviate. Using this baseline, an early packet or a late packet can be detected. An early packet pushes the baseline down to that earlier point, while late arriving packets, if they are arriving late for acontinuous period of time, represents a shift in the opposite direction from the baseline, resulting in a baseline moving to the ''earliest'' packet out of the sequence of the late arriving packets.

Description

technical field [0001] An exemplary embodiment of the present invention relates to networking devices, services and methods, and more particularly to clock management between two endpoints. Background technique [0002] Devices on a network, such as a packet-switched network, typically use an internal clock to determine timing information at runtime. This means that the sending device's clock and the receiving device's clock can be out of sync. Typically, these devices transfer data, and differences in clock rates between different devices do not cause problems. Arbitrary size buffers can be utilized, and long timeouts can be programmed to ensure that all received data is stored. However, real-time data such as voice, fax, video, modem communications, etc. can be interactive in nature, with short timeouts and delays. This type of data greatly benefits from having synchronized clocks between the transmitter and receiver. [0003] At the receiver, an internal clock is used...

Claims

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Application Information

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IPC IPC(8): H04L7/00H04L29/06
CPCH04J3/0664H04N21/4305H04N21/6437H04N21/8547H04L7/02
Inventor L·D·吉本斯L·A·图卡A·斯高特M-S·昂
Owner AVAYA TECH LLC