Watchdog reset circuit and reset method
A reset circuit and watchdog technology, applied in data reset devices, electrical digital data processing, instruments, etc., can solve problems such as the failure of the watchdog circuit and the inability of the watchdog circuit to work.
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- Publication Date
- 2009-02-18
Smart Images
Figure 1 Figure 2 Figure 3
Abstract
Description
technical field
[0001] The present invention relates to the field of electronic data processing (G06) and the field of electric communication technology (H04), in particular to a watchdog reset circuit and a reset method. Background technique
[0002] At present, most single boards on the base station have chips such as CPU, watchdog, and EPLD. Among them, the CPU is the brain of the board management and maintenance, and the EPLD acts as address decoding, chip selection and reset distribution, and cooperates with the watchdog and other functions. The version of EPLD is burnt in at one time after the realization of the single board. There are various ways to realize the watchdog circuit of the single board, but the general idea is that the CPU extends the dog feeding time through EPLD, which prolongs the reset time of the watchdog chip. However, as the capacity of EPLD chips continues to increase, EPLDs perform more and more functions. In order to improve design flexibility...
Examples
Embodiment Construction
[0019] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0020] Such as figure 1 As shown, in the watchdog reset circuit that the watchdog circuit still works normally during the upgrade of the programmable device, the present invention is provided with more than two programmable devices, and the second new programmable device is to upgrade the programmable device It acts as a temporary watchdog during the version period and is another watchdog, so the watchdog circuit provided by the present invention can also be regarded as a multi-watchdog reset circuit. figure 1 With two programmable devices shown, the multi-watchdog circuit consists of the following blocks:
[0021] The CPU processor is connected to the programmable device through the bus, and receives the power-on reset signal (Power_Reset) sent by the watchdog circuit;
[0022] Programmable device 1, used to cooperate with the watc...