APB bus cross-clock field access circuit and method

Abstract

The present invention relates to an APB cross-clock domain access circuit, which comprises an APB bridge, a control register and a clock synchronous circuit. The APB bridge serves as a control terminal of the APB and works in the APB clock domain; the control register serves as an accessed terminal of the APB and works in the clock domain of the accessed terminal; the clock synchronization circuit is used for synchronizing chip selection signals (psel) and enabling signals (penable) of the APB clock domain into the clock domain of the accessed terminal and outputting the signals to the control register as control signals (msel); and then the control signals (msel) are synchronized into the APB clock domain and transmitted backwards to the APB bridge as handshaking signal (pready). With the APB bus and the register in the module arranged at the cross-clock domain and the combination with the APB 3.0 access handshaking method, the present invention ensures that the clock of the control register of the module is arranged in the module, eliminates the risk that the register in the module and the inner state of the register are unstable, and simultaneously reduces the relevant hardwareoverhead and access delay.

Description

technical field [0001] The invention relates to a circuit and a method for cross-clock domain access of an APB bus. Background technique [0002] There are multiple functional modules in a System-on-Chip (SoC), such as processors and various hardware modules. The processor controls the operation of the hardware modules by modifying the internal control registers of each hardware module. Meanwhile, in order to reduce power consumption, various hardware modules and processors may operate at different clock frequencies. For example, computing-intensive modules need to work on high-frequency clocks, while modules such as port transmission may work on lower clock frequencies. Therefore, when the processor configures the control registers inside the module, it needs to consider the behavior across clock domains. Traditionally, the processor accesses various registers inside the module through some general-purpose bus, such as the APB bus. [0003] figure 1 It is a schematic d...

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Problems solved by technology

However, this method needs to ensure that the configuration of the registers is completed at one time each time, and if the processor wants to detect the operating status of the module, it may read an uncertain status, which increases the potential error risk of the system

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