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Bus logical gateway circuit of plurality of break request signals

A technology for requesting signals and gateways, applied in the fields of electrical digital data processing, instruments, etc., which can solve the problems of signal detection leakage, increasing the burden of computer systems, and unfavorable development of industry and manufacturer systems.

Active Publication Date: 2010-08-11
TRENDON TOUCH TECHNOLOGY CORPORATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] This known method not only has the problem of signal detection leakage in the processing of interrupt request signals, but even if each interrupt request signal is processed normally, its processing speed is also slow
And in the actual system application, it will increase the burden on the computer system when processing the interrupt request signal, and it is not conducive to the system development of the manufacturer.

Method used

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  • Bus logical gateway circuit of plurality of break request signals
  • Bus logical gateway circuit of plurality of break request signals
  • Bus logical gateway circuit of plurality of break request signals

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Embodiment Construction

[0029] As shown in FIG. 2 , it shows the circuit connection diagram between the bus logic gateway circuit 100 of the present invention and the device-end interrupt request signals D1_INT, D2_INT, D3_INT...Dn_INT sent by several ISA devices and the ISA bus 23 . Each device-end interrupt request signal D1_INT, D2_INT, D3_INT...Dn_INT is sent to the ISA bus 23 after passing through the bus logic gateway circuit 100 of the present invention.

[0030] Referring to FIG. 3 , it is a further circuit diagram showing the bus logic gateway circuit 100 of the present invention. FIG. 4 is a schematic waveform diagram showing the interrupt request signals D1_INT, D2_INT, D3_INT . . . D8_INT3 of each device in FIG.

[0031] Please also refer to FIG. 2-FIG. 4, the bus logic gateway circuit 100 of the present invention includes several gateway circuits 3a, 3b...3n. The device-end interrupt request signals D1_INT, D2_INT, D3_INT...Dn_INT generated by each target device are respectively sent to...

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PUM

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Abstract

The invention relates to a bus logical gateway circuit for a plurality of interruption request signals which comprises the following components: an output alternation gate which is provided with a plurality of input ends and an interruption request signal output end; a reverser which is provided with an input end and an output end; wherein, the input end is the interruption request signal output end connected to the output alternation gate; a plurality of gateway circuits used for leading the device end interruption request signals generated by a plurality of target devices to pass the gateway circuits or temporarily maintain in the gateway circuits. Each gateway circuit includes an AND gate and an alternation gate; according to the state of the output end of the AND gate and the interruption request signal output end of the output alternation gate, the alternation gate generates a gateway signal and transmits the signal to the gateway signal input end of the AND gate.

Description

technical field [0001] The invention relates to a processing circuit for interrupt request signals, in particular to a bus interface processing circuit for a plurality of interrupt request signals of a computer system. Background technique [0002] In a typical computer system or digital system structure, it mainly includes hardware components such as a central processing unit, a disk device, an input device, an output device, and a memory. These hardware components are connected, data transmitted, and controlled by a bus. In today's bus specifications, there are many different bus specifications and types according to different system requirements and characteristics. [0003] Referring first to FIG. 1 , it is a block diagram showing a computer system or digital system including an ISA bus. A typical computer system includes a central processing unit 11, a memory 12, a PCI bridge 13 (PCI Bridge), at least one PCI device 14, a PCI / ISA bridge 15 (PCI / ISA Bridge), several IS...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/24
Inventor 黄尧熙
Owner TRENDON TOUCH TECHNOLOGY CORPORATION