Bus logical gateway circuit of plurality of break request signals
A technology for requesting signals and gateways, applied in the fields of electrical digital data processing, instruments, etc., which can solve the problems of signal detection leakage, increasing the burden of computer systems, and unfavorable development of industry and manufacturer systems.
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[0029] As shown in FIG. 2 , it shows the circuit connection diagram between the bus logic gateway circuit 100 of the present invention and the device-end interrupt request signals D1_INT, D2_INT, D3_INT...Dn_INT sent by several ISA devices and the ISA bus 23 . Each device-end interrupt request signal D1_INT, D2_INT, D3_INT...Dn_INT is sent to the ISA bus 23 after passing through the bus logic gateway circuit 100 of the present invention.
[0030] Referring to FIG. 3 , it is a further circuit diagram showing the bus logic gateway circuit 100 of the present invention. FIG. 4 is a schematic waveform diagram showing the interrupt request signals D1_INT, D2_INT, D3_INT . . . D8_INT3 of each device in FIG.
[0031] Please also refer to FIG. 2-FIG. 4, the bus logic gateway circuit 100 of the present invention includes several gateway circuits 3a, 3b...3n. The device-end interrupt request signals D1_INT, D2_INT, D3_INT...Dn_INT generated by each target device are respectively sent to...
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